derek.holloway
7502bf64a4
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376 lines
21 KiB
LLVM
376 lines
21 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s
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; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s
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declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float %scale)
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declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float %scale)
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declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> %src, float %scale)
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declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %src, float %scale)
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declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %src, float %scale)
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declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float %scale)
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define amdgpu_ps void @test_scalef32_pk16_bf6_f32_vv(<16 x float> %src, float %scale, ptr addrspace(1) %out) {
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; GFX1210-SDAG-LABEL: test_scalef32_pk16_bf6_f32_vv:
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; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_vv:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v23, v18 :: v_dual_mov_b32 v22, v17
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; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[0:15], v16
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; GFX1250-SDAG-NEXT: global_store_b96 v[22:23], v[18:20], off
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f32_vv:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v22, v17 :: v_dual_mov_b32 v23, v18
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; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[0:15], v16
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; GFX1250-GISEL-NEXT: global_store_b96 v[22:23], v[18:20], off
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; GFX1250-GISEL-NEXT: s_endpgm
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%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float %scale)
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store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_pk16_bf6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) {
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; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_sl:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15
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; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[2:17], 0x42c80000
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; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f32_sl:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[2:17], 0x42c80000
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; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off
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; GFX1250-GISEL-NEXT: s_endpgm
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%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float 100.0)
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store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_pk16_fp6_f32_vv(<16 x float> %src, float %scale, ptr addrspace(1) %out) {
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; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f32_vv:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v23, v18 :: v_dual_mov_b32 v22, v17
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; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[0:15], v16
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; GFX1250-SDAG-NEXT: global_store_b96 v[22:23], v[18:20], off
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f32_vv:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v22, v17 :: v_dual_mov_b32 v23, v18
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; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[0:15], v16
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; GFX1250-GISEL-NEXT: global_store_b96 v[22:23], v[18:20], off
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; GFX1250-GISEL-NEXT: s_endpgm
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%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float %scale)
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store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_pk16_fp6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) {
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; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f32_sl:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15
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; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[2:17], 0x42c80000
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; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f32_sl:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
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; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[2:17], 0x42c80000
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; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off
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; GFX1250-GISEL-NEXT: s_endpgm
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%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float 100.0)
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store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_vv(<16 x bfloat> %src, float %scale, ptr addrspace(1) %out) {
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; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_bf16_vv:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
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; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[0:7], v8
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; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_bf16_vv:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
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; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[0:7], v8
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; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off
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; GFX1250-GISEL-NEXT: s_endpgm
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%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> %src, float %scale)
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store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_pk16_bf6_bf16_sl(<16 x bfloat> inreg %src, ptr addrspace(1) %out) {
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; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_bf16_sl:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
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; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
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; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[2:9], 0x42c80000
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; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_bf16_sl:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
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; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_bf16 v[10:12], v[2:9], 0x42c80000
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; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off
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; GFX1250-GISEL-NEXT: s_endpgm
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%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.bf16(<16 x bfloat> %src, float 100.0)
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|
store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_scalef32_pk16_bf6_f16_vv(<16 x half> %src, float %scale, ptr addrspace(1) %out) {
|
|
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f16_vv:
|
|
; GFX1250-SDAG: ; %bb.0:
|
|
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-SDAG-NEXT: v_nop
|
|
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
|
|
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[0:7], v8
|
|
; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off
|
|
; GFX1250-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f16_vv:
|
|
; GFX1250-GISEL: ; %bb.0:
|
|
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-GISEL-NEXT: v_nop
|
|
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v14, v9 :: v_dual_mov_b32 v15, v10
|
|
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[0:7], v8
|
|
; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off
|
|
; GFX1250-GISEL-NEXT: s_endpgm
|
|
%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %src, float %scale)
|
|
store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_scalef32_pk16_bf6_f16_sl(<16 x half> inreg %src, ptr addrspace(1) %out) {
|
|
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f16_sl:
|
|
; GFX1250-SDAG: ; %bb.0:
|
|
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-SDAG-NEXT: v_nop
|
|
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
|
|
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[2:9], 0x42c80000
|
|
; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off
|
|
; GFX1250-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f16_sl:
|
|
; GFX1250-GISEL: ; %bb.0:
|
|
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-GISEL-NEXT: v_nop
|
|
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
|
|
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
|
|
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
|
|
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
|
|
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[2:9], 0x42c80000
|
|
; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off
|
|
; GFX1250-GISEL-NEXT: s_endpgm
|
|
%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %src, float 100.0)
|
|
store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_vv(<16 x bfloat> %src, float %scale, ptr addrspace(1) %out) {
|
|
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_bf16_vv:
|
|
; GFX1250-SDAG: ; %bb.0:
|
|
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-SDAG-NEXT: v_nop
|
|
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
|
|
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[0:7], v8
|
|
; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off
|
|
; GFX1250-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_bf16_vv:
|
|
; GFX1250-GISEL: ; %bb.0:
|
|
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-GISEL-NEXT: v_nop
|
|
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
|
|
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[0:7], v8
|
|
; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off
|
|
; GFX1250-GISEL-NEXT: s_endpgm
|
|
%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %src, float %scale)
|
|
store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_scalef32_pk16_fp6_bf16_sl(<16 x bfloat> inreg %src, ptr addrspace(1) %out) {
|
|
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_bf16_sl:
|
|
; GFX1250-SDAG: ; %bb.0:
|
|
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-SDAG-NEXT: v_nop
|
|
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
|
|
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[2:9], 0x42c80000
|
|
; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off
|
|
; GFX1250-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_bf16_sl:
|
|
; GFX1250-GISEL: ; %bb.0:
|
|
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-GISEL-NEXT: v_nop
|
|
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
|
|
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
|
|
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
|
|
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
|
|
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_bf16 v[10:12], v[2:9], 0x42c80000
|
|
; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off
|
|
; GFX1250-GISEL-NEXT: s_endpgm
|
|
%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.bf16(<16 x bfloat> %src, float 100.0)
|
|
store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_scalef32_pk16_fp6_f16_vv(<16 x half> %src, float %scale, ptr addrspace(1) %out) {
|
|
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f16_vv:
|
|
; GFX1250-SDAG: ; %bb.0:
|
|
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-SDAG-NEXT: v_nop
|
|
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v15, v10 :: v_dual_mov_b32 v14, v9
|
|
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[0:7], v8
|
|
; GFX1250-SDAG-NEXT: global_store_b96 v[14:15], v[10:12], off
|
|
; GFX1250-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f16_vv:
|
|
; GFX1250-GISEL: ; %bb.0:
|
|
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-GISEL-NEXT: v_nop
|
|
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v14, v9 :: v_dual_mov_b32 v15, v10
|
|
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[0:7], v8
|
|
; GFX1250-GISEL-NEXT: global_store_b96 v[14:15], v[10:12], off
|
|
; GFX1250-GISEL-NEXT: s_endpgm
|
|
%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float %scale)
|
|
store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_scalef32_pk16_fp6_f16_sl(<16 x half> inreg %src, ptr addrspace(1) %out) {
|
|
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f16_sl:
|
|
; GFX1250-SDAG: ; %bb.0:
|
|
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-SDAG-NEXT: v_nop
|
|
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
|
|
; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
|
|
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[2:9], 0x42c80000
|
|
; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off
|
|
; GFX1250-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f16_sl:
|
|
; GFX1250-GISEL: ; %bb.0:
|
|
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-GISEL-NEXT: v_nop
|
|
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
|
|
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
|
|
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
|
|
; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
|
|
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[2:9], 0x42c80000
|
|
; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off
|
|
; GFX1250-GISEL-NEXT: s_endpgm
|
|
%cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float 100.0)
|
|
store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|