derek.holloway
7502bf64a4
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317 lines
14 KiB
LLVM
317 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GCN,GFX950-SDAG %s
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; RUN: llc -global-isel=1 -global-isel-abort=2 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GCN,GFX950-GISEL %s
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declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)
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declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f16(<32 x half> %src, i32 %sr, float %scale)
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declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f32(<32 x float> %src, i32 %sr, float %scale)
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declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)
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declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f16(<32 x half> %src, i32 %sr, float %scale)
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declare <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f32(<32 x float> %src, i32 %sr, float %scale)
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define amdgpu_ps void @test_scalef32_sr_pk32_bf6_bf16_vv(<32 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
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; GCN-LABEL: test_scalef32_sr_pk32_bf6_bf16_vv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[20:25], v[0:15], v16, v17
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; GCN-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
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; GCN-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
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; GCN-NEXT: s_endpgm
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%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)
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store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk32_bf6_bf16_sl(<32 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
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; GCN-LABEL: test_scalef32_sr_pk32_bf6_bf16_sl:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v2, s0
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; GCN-NEXT: v_mov_b32_e32 v3, s1
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; GCN-NEXT: v_mov_b32_e32 v4, s2
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; GCN-NEXT: v_mov_b32_e32 v5, s3
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; GCN-NEXT: v_mov_b32_e32 v6, s4
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; GCN-NEXT: v_mov_b32_e32 v7, s5
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; GCN-NEXT: v_mov_b32_e32 v8, s6
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; GCN-NEXT: v_mov_b32_e32 v9, s7
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; GCN-NEXT: v_mov_b32_e32 v10, s8
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; GCN-NEXT: v_mov_b32_e32 v11, s9
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; GCN-NEXT: v_mov_b32_e32 v12, s10
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; GCN-NEXT: v_mov_b32_e32 v13, s11
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; GCN-NEXT: v_mov_b32_e32 v14, s12
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; GCN-NEXT: v_mov_b32_e32 v15, s13
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; GCN-NEXT: v_mov_b32_e32 v16, s14
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; GCN-NEXT: v_mov_b32_e32 v17, s15
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; GCN-NEXT: v_mov_b32_e32 v24, 0x42c80000
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; GCN-NEXT: v_cvt_scalef32_sr_pk32_bf6_bf16 v[18:23], v[2:17], s16, v24
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; GCN-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
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; GCN-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
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; GCN-NEXT: s_endpgm
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%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.bf16(<32 x bfloat> %src, i32 %sr, float 100.0)
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store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f16_vv(<32 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
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; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_f16_vv:
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; GFX950-SDAG: ; %bb.0:
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; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_f16 v[20:25], v[0:15], v16, v17
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; GFX950-SDAG-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
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; GFX950-SDAG-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
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; GFX950-SDAG-NEXT: s_endpgm
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;
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; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_f16_vv:
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; GFX950-GISEL: ; %bb.0:
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; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_f16 v[20:25], v[0:15], v16, v17
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; GFX950-GISEL-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
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; GFX950-GISEL-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
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; GFX950-GISEL-NEXT: s_endpgm
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%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f16(<32 x half> %src, i32 %sr, float %scale)
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store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f16_sl(<32 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
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; GCN-LABEL: test_scalef32_sr_pk32_bf6_f16_sl:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v2, s0
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; GCN-NEXT: v_mov_b32_e32 v3, s1
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; GCN-NEXT: v_mov_b32_e32 v4, s2
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; GCN-NEXT: v_mov_b32_e32 v5, s3
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; GCN-NEXT: v_mov_b32_e32 v6, s4
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; GCN-NEXT: v_mov_b32_e32 v7, s5
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; GCN-NEXT: v_mov_b32_e32 v8, s6
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; GCN-NEXT: v_mov_b32_e32 v9, s7
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; GCN-NEXT: v_mov_b32_e32 v10, s8
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; GCN-NEXT: v_mov_b32_e32 v11, s9
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; GCN-NEXT: v_mov_b32_e32 v12, s10
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; GCN-NEXT: v_mov_b32_e32 v13, s11
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; GCN-NEXT: v_mov_b32_e32 v14, s12
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; GCN-NEXT: v_mov_b32_e32 v15, s13
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; GCN-NEXT: v_mov_b32_e32 v16, s14
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; GCN-NEXT: v_mov_b32_e32 v17, s15
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; GCN-NEXT: v_mov_b32_e32 v24, 0x42c80000
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; GCN-NEXT: v_cvt_scalef32_sr_pk32_bf6_f16 v[18:23], v[2:17], s16, v24
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; GCN-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
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; GCN-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
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; GCN-NEXT: s_endpgm
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%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f16(<32 x half> %src, i32 %sr, float 100.0)
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store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk32_fp6_bf16_vv(<32 x bfloat> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
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; GCN-LABEL: test_scalef32_sr_pk32_fp6_bf16_vv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[20:25], v[0:15], v16, v17
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; GCN-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
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; GCN-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
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; GCN-NEXT: s_endpgm
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%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.bf16(<32 x bfloat> %src, i32 %sr, float %scale)
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store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk32_fp6_bf16_sl(<32 x bfloat> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
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; GCN-LABEL: test_scalef32_sr_pk32_fp6_bf16_sl:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v2, s0
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; GCN-NEXT: v_mov_b32_e32 v3, s1
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; GCN-NEXT: v_mov_b32_e32 v4, s2
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; GCN-NEXT: v_mov_b32_e32 v5, s3
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; GCN-NEXT: v_mov_b32_e32 v6, s4
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; GCN-NEXT: v_mov_b32_e32 v7, s5
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; GCN-NEXT: v_mov_b32_e32 v8, s6
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; GCN-NEXT: v_mov_b32_e32 v9, s7
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; GCN-NEXT: v_mov_b32_e32 v10, s8
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; GCN-NEXT: v_mov_b32_e32 v11, s9
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; GCN-NEXT: v_mov_b32_e32 v12, s10
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; GCN-NEXT: v_mov_b32_e32 v13, s11
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; GCN-NEXT: v_mov_b32_e32 v14, s12
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; GCN-NEXT: v_mov_b32_e32 v15, s13
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; GCN-NEXT: v_mov_b32_e32 v16, s14
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; GCN-NEXT: v_mov_b32_e32 v17, s15
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; GCN-NEXT: v_mov_b32_e32 v24, 0x42c80000
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; GCN-NEXT: v_cvt_scalef32_sr_pk32_fp6_bf16 v[18:23], v[2:17], s16, v24
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; GCN-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
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; GCN-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
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; GCN-NEXT: s_endpgm
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%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.bf16(<32 x bfloat> %src, i32 %sr, float 100.0)
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store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f16_vv(<32 x half> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
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; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_f16_vv:
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; GFX950-SDAG: ; %bb.0:
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; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_f16 v[20:25], v[0:15], v16, v17
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; GFX950-SDAG-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
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; GFX950-SDAG-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
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; GFX950-SDAG-NEXT: s_endpgm
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;
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; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_f16_vv:
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; GFX950-GISEL: ; %bb.0:
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; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_f16 v[20:25], v[0:15], v16, v17
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; GFX950-GISEL-NEXT: global_store_dwordx4 v[18:19], v[20:23], off
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; GFX950-GISEL-NEXT: global_store_dwordx2 v[18:19], v[24:25], off offset:16
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; GFX950-GISEL-NEXT: s_endpgm
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%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f16(<32 x half> %src, i32 %sr, float %scale)
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store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f16_sl(<32 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
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; GCN-LABEL: test_scalef32_sr_pk32_fp6_f16_sl:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v2, s0
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; GCN-NEXT: v_mov_b32_e32 v3, s1
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; GCN-NEXT: v_mov_b32_e32 v4, s2
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; GCN-NEXT: v_mov_b32_e32 v5, s3
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; GCN-NEXT: v_mov_b32_e32 v6, s4
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; GCN-NEXT: v_mov_b32_e32 v7, s5
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; GCN-NEXT: v_mov_b32_e32 v8, s6
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; GCN-NEXT: v_mov_b32_e32 v9, s7
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; GCN-NEXT: v_mov_b32_e32 v10, s8
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; GCN-NEXT: v_mov_b32_e32 v11, s9
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; GCN-NEXT: v_mov_b32_e32 v12, s10
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; GCN-NEXT: v_mov_b32_e32 v13, s11
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; GCN-NEXT: v_mov_b32_e32 v14, s12
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; GCN-NEXT: v_mov_b32_e32 v15, s13
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; GCN-NEXT: v_mov_b32_e32 v16, s14
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; GCN-NEXT: v_mov_b32_e32 v17, s15
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; GCN-NEXT: v_mov_b32_e32 v24, 0x42c80000
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; GCN-NEXT: v_cvt_scalef32_sr_pk32_fp6_f16 v[18:23], v[2:17], s16, v24
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; GCN-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
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; GCN-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
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; GCN-NEXT: s_endpgm
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%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f16(<32 x half> %src, i32 %sr, float 100.0)
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store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f32_vv(<32 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
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; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_bf6_f32_vv:
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; GFX950-SDAG: ; %bb.0:
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; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_bf6_f32 v[36:41], v[0:31], v32, v33
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; GFX950-SDAG-NEXT: global_store_dwordx2 v[34:35], v[40:41], off offset:16
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; GFX950-SDAG-NEXT: global_store_dwordx4 v[34:35], v[36:39], off
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; GFX950-SDAG-NEXT: s_endpgm
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;
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; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_bf6_f32_vv:
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; GFX950-GISEL: ; %bb.0:
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; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_bf6_f32 v[36:41], v[0:31], v32, v33
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; GFX950-GISEL-NEXT: global_store_dwordx4 v[34:35], v[36:39], off
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; GFX950-GISEL-NEXT: global_store_dwordx2 v[34:35], v[40:41], off offset:16
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; GFX950-GISEL-NEXT: s_endpgm
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%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f32(<32 x float> %src, i32 %sr, float %scale)
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store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_ps void @test_scalef32_sr_pk32_bf6_f32_sl(<32 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
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; GCN-LABEL: test_scalef32_sr_pk32_bf6_f32_sl:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v2, s0
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; GCN-NEXT: v_mov_b32_e32 v3, s1
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; GCN-NEXT: v_mov_b32_e32 v4, s2
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; GCN-NEXT: v_mov_b32_e32 v5, s3
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; GCN-NEXT: v_mov_b32_e32 v6, s4
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; GCN-NEXT: v_mov_b32_e32 v7, s5
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; GCN-NEXT: v_mov_b32_e32 v8, s6
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; GCN-NEXT: v_mov_b32_e32 v9, s7
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; GCN-NEXT: v_mov_b32_e32 v10, s8
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; GCN-NEXT: v_mov_b32_e32 v11, s9
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; GCN-NEXT: v_mov_b32_e32 v12, s10
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; GCN-NEXT: v_mov_b32_e32 v13, s11
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; GCN-NEXT: v_mov_b32_e32 v14, s12
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; GCN-NEXT: v_mov_b32_e32 v15, s13
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; GCN-NEXT: v_mov_b32_e32 v16, s14
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; GCN-NEXT: v_mov_b32_e32 v17, s15
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; GCN-NEXT: v_mov_b32_e32 v18, s16
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; GCN-NEXT: v_mov_b32_e32 v19, s17
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; GCN-NEXT: v_mov_b32_e32 v20, s18
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; GCN-NEXT: v_mov_b32_e32 v21, s19
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; GCN-NEXT: v_mov_b32_e32 v22, s20
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; GCN-NEXT: v_mov_b32_e32 v23, s21
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; GCN-NEXT: v_mov_b32_e32 v24, s22
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; GCN-NEXT: v_mov_b32_e32 v25, s23
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; GCN-NEXT: v_mov_b32_e32 v26, s24
|
|
; GCN-NEXT: v_mov_b32_e32 v27, s25
|
|
; GCN-NEXT: v_mov_b32_e32 v28, s26
|
|
; GCN-NEXT: v_mov_b32_e32 v29, s27
|
|
; GCN-NEXT: v_mov_b32_e32 v30, s28
|
|
; GCN-NEXT: v_mov_b32_e32 v31, s29
|
|
; GCN-NEXT: v_mov_b32_e32 v32, s30
|
|
; GCN-NEXT: v_mov_b32_e32 v33, s31
|
|
; GCN-NEXT: v_mov_b32_e32 v40, 0x42c80000
|
|
; GCN-NEXT: v_cvt_scalef32_sr_pk32_bf6_f32 v[34:39], v[2:33], s32, v40
|
|
; GCN-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16
|
|
; GCN-NEXT: global_store_dwordx4 v[0:1], v[34:37], off
|
|
; GCN-NEXT: s_endpgm
|
|
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.bf6.f32(<32 x float> %src, i32 %sr, float 100.0)
|
|
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f32_vv(<32 x float> %src, i32 %sr, float %scale, ptr addrspace(1) %out) {
|
|
; GFX950-SDAG-LABEL: test_scalef32_sr_pk32_fp6_f32_vv:
|
|
; GFX950-SDAG: ; %bb.0:
|
|
; GFX950-SDAG-NEXT: v_cvt_scalef32_sr_pk32_fp6_f32 v[36:41], v[0:31], v32, v33
|
|
; GFX950-SDAG-NEXT: global_store_dwordx2 v[34:35], v[40:41], off offset:16
|
|
; GFX950-SDAG-NEXT: global_store_dwordx4 v[34:35], v[36:39], off
|
|
; GFX950-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX950-GISEL-LABEL: test_scalef32_sr_pk32_fp6_f32_vv:
|
|
; GFX950-GISEL: ; %bb.0:
|
|
; GFX950-GISEL-NEXT: v_cvt_scalef32_sr_pk32_fp6_f32 v[36:41], v[0:31], v32, v33
|
|
; GFX950-GISEL-NEXT: global_store_dwordx4 v[34:35], v[36:39], off
|
|
; GFX950-GISEL-NEXT: global_store_dwordx2 v[34:35], v[40:41], off offset:16
|
|
; GFX950-GISEL-NEXT: s_endpgm
|
|
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f32(<32 x float> %src, i32 %sr, float %scale)
|
|
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @test_scalef32_sr_pk32_fp6_f32_sl(<32 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
|
|
; GCN-LABEL: test_scalef32_sr_pk32_fp6_f32_sl:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: v_mov_b32_e32 v2, s0
|
|
; GCN-NEXT: v_mov_b32_e32 v3, s1
|
|
; GCN-NEXT: v_mov_b32_e32 v4, s2
|
|
; GCN-NEXT: v_mov_b32_e32 v5, s3
|
|
; GCN-NEXT: v_mov_b32_e32 v6, s4
|
|
; GCN-NEXT: v_mov_b32_e32 v7, s5
|
|
; GCN-NEXT: v_mov_b32_e32 v8, s6
|
|
; GCN-NEXT: v_mov_b32_e32 v9, s7
|
|
; GCN-NEXT: v_mov_b32_e32 v10, s8
|
|
; GCN-NEXT: v_mov_b32_e32 v11, s9
|
|
; GCN-NEXT: v_mov_b32_e32 v12, s10
|
|
; GCN-NEXT: v_mov_b32_e32 v13, s11
|
|
; GCN-NEXT: v_mov_b32_e32 v14, s12
|
|
; GCN-NEXT: v_mov_b32_e32 v15, s13
|
|
; GCN-NEXT: v_mov_b32_e32 v16, s14
|
|
; GCN-NEXT: v_mov_b32_e32 v17, s15
|
|
; GCN-NEXT: v_mov_b32_e32 v18, s16
|
|
; GCN-NEXT: v_mov_b32_e32 v19, s17
|
|
; GCN-NEXT: v_mov_b32_e32 v20, s18
|
|
; GCN-NEXT: v_mov_b32_e32 v21, s19
|
|
; GCN-NEXT: v_mov_b32_e32 v22, s20
|
|
; GCN-NEXT: v_mov_b32_e32 v23, s21
|
|
; GCN-NEXT: v_mov_b32_e32 v24, s22
|
|
; GCN-NEXT: v_mov_b32_e32 v25, s23
|
|
; GCN-NEXT: v_mov_b32_e32 v26, s24
|
|
; GCN-NEXT: v_mov_b32_e32 v27, s25
|
|
; GCN-NEXT: v_mov_b32_e32 v28, s26
|
|
; GCN-NEXT: v_mov_b32_e32 v29, s27
|
|
; GCN-NEXT: v_mov_b32_e32 v30, s28
|
|
; GCN-NEXT: v_mov_b32_e32 v31, s29
|
|
; GCN-NEXT: v_mov_b32_e32 v32, s30
|
|
; GCN-NEXT: v_mov_b32_e32 v33, s31
|
|
; GCN-NEXT: v_mov_b32_e32 v40, 0x42c80000
|
|
; GCN-NEXT: v_cvt_scalef32_sr_pk32_fp6_f32 v[34:39], v[2:33], s32, v40
|
|
; GCN-NEXT: global_store_dwordx2 v[0:1], v[38:39], off offset:16
|
|
; GCN-NEXT: global_store_dwordx4 v[0:1], v[34:37], off
|
|
; GCN-NEXT: s_endpgm
|
|
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk32.fp6.f32(<32 x float> %src, i32 %sr, float 100.0)
|
|
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|