derek.holloway
7502bf64a4
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301 lines
9.9 KiB
LLVM
301 lines
9.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "load" --filter-out "store" --filter-out "wait" --version 6
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-GISEL %s
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declare half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c)
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define amdgpu_kernel void @div_fixup_f16(
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; VI-SDAG-LABEL: div_fixup_f16:
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; VI-SDAG: ; %bb.0: ; %entry
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; VI-SDAG: s_mov_b32 s11, 0xf000
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; VI-SDAG: s_mov_b32 s10, -1
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; VI-SDAG: s_mov_b32 s14, s10
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; VI-SDAG: s_mov_b32 s15, s11
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; VI-SDAG: s_mov_b32 s12, s2
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; VI-SDAG: s_mov_b32 s13, s3
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; VI-SDAG: s_mov_b32 s16, s4
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; VI-SDAG: s_mov_b32 s17, s5
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; VI-SDAG: s_mov_b32 s18, s10
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; VI-SDAG: s_mov_b32 s19, s11
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; VI-SDAG: s_mov_b32 s4, s6
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; VI-SDAG: s_mov_b32 s5, s7
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; VI-SDAG: s_mov_b32 s6, s10
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; VI-SDAG: s_mov_b32 s7, s11
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; VI-SDAG: s_mov_b32 s8, s0
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; VI-SDAG: s_mov_b32 s9, s1
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; VI-SDAG: v_div_fixup_f16 v0, v0, v1, v2
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; VI-SDAG: s_endpgm
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;
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; VI-GISEL-LABEL: div_fixup_f16:
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; VI-GISEL: ; %bb.0: ; %entry
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; VI-GISEL: s_mov_b32 s10, -1
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; VI-GISEL: s_mov_b32 s11, 0xf000
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; VI-GISEL: s_mov_b64 s[8:9], s[2:3]
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; VI-GISEL: s_mov_b64 s[8:9], s[4:5]
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; VI-GISEL: s_mov_b64 s[8:9], s[6:7]
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; VI-GISEL: v_readfirstlane_b32 s2, v0
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; VI-GISEL: v_readfirstlane_b32 s3, v1
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; VI-GISEL: v_mov_b32_e32 v0, s3
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; VI-GISEL: v_readfirstlane_b32 s4, v2
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; VI-GISEL: v_mov_b32_e32 v1, s4
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; VI-GISEL: v_div_fixup_f16 v0, s2, v0, v1
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; VI-GISEL: s_mov_b64 s[2:3], s[10:11]
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; VI-GISEL: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load volatile half, ptr addrspace(1) %a
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%b.val = load volatile half, ptr addrspace(1) %b
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%c.val = load volatile half, ptr addrspace(1) %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half %b.val, half %c.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @div_fixup_f16_imm_a(
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; VI-SDAG-LABEL: div_fixup_f16_imm_a:
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; VI-SDAG: ; %bb.0: ; %entry
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; VI-SDAG: s_mov_b32 s7, 0xf000
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; VI-SDAG: s_mov_b32 s6, -1
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; VI-SDAG: s_mov_b32 s14, s6
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; VI-SDAG: s_mov_b32 s12, s2
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; VI-SDAG: s_mov_b32 s13, s3
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; VI-SDAG: s_mov_b32 s15, s7
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; VI-SDAG: s_mov_b32 s10, s6
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; VI-SDAG: s_mov_b32 s11, s7
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; VI-SDAG: s_mov_b32 s4, s0
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; VI-SDAG: s_movk_i32 s0, 0x4200
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; VI-SDAG: s_mov_b32 s5, s1
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; VI-SDAG: v_div_fixup_f16 v0, s0, v0, v1
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; VI-SDAG: s_endpgm
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;
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; VI-GISEL-LABEL: div_fixup_f16_imm_a:
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; VI-GISEL: ; %bb.0: ; %entry
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; VI-GISEL: s_mov_b32 s6, -1
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; VI-GISEL: s_mov_b32 s7, 0xf000
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; VI-GISEL: s_mov_b64 s[10:11], s[6:7]
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; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
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; VI-GISEL: v_mov_b32_e32 v2, 0x4200
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; VI-GISEL: v_readfirstlane_b32 s2, v0
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; VI-GISEL: v_readfirstlane_b32 s3, v1
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; VI-GISEL: v_mov_b32_e32 v0, s3
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; VI-GISEL: v_div_fixup_f16 v0, v2, s2, v0
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; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
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; VI-GISEL: s_nop 1
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; VI-GISEL: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%b.val = load volatile half, ptr addrspace(1) %b
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%c.val = load volatile half, ptr addrspace(1) %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half %b.val, half %c.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @div_fixup_f16_imm_b(
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; VI-SDAG-LABEL: div_fixup_f16_imm_b:
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; VI-SDAG: ; %bb.0: ; %entry
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; VI-SDAG: s_mov_b32 s7, 0xf000
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; VI-SDAG: s_mov_b32 s6, -1
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; VI-SDAG: s_mov_b32 s14, s6
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; VI-SDAG: s_mov_b32 s12, s2
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; VI-SDAG: s_mov_b32 s13, s3
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; VI-SDAG: s_mov_b32 s15, s7
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; VI-SDAG: s_mov_b32 s10, s6
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; VI-SDAG: s_mov_b32 s11, s7
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; VI-SDAG: s_mov_b32 s4, s0
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; VI-SDAG: s_movk_i32 s0, 0x4200
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; VI-SDAG: s_mov_b32 s5, s1
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; VI-SDAG: v_div_fixup_f16 v0, v0, s0, v1
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; VI-SDAG: s_endpgm
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;
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; VI-GISEL-LABEL: div_fixup_f16_imm_b:
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; VI-GISEL: ; %bb.0: ; %entry
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; VI-GISEL: s_mov_b32 s6, -1
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; VI-GISEL: s_mov_b32 s7, 0xf000
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; VI-GISEL: s_mov_b64 s[10:11], s[6:7]
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; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
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; VI-GISEL: v_mov_b32_e32 v2, 0x4200
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; VI-GISEL: v_readfirstlane_b32 s2, v0
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; VI-GISEL: v_readfirstlane_b32 s3, v1
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; VI-GISEL: v_mov_b32_e32 v0, s3
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; VI-GISEL: v_div_fixup_f16 v0, s2, v2, v0
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; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
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; VI-GISEL: s_nop 1
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; VI-GISEL: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load volatile half, ptr addrspace(1) %a
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%c.val = load volatile half, ptr addrspace(1) %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half 3.0, half %c.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @div_fixup_f16_imm_c(
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; VI-SDAG-LABEL: div_fixup_f16_imm_c:
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; VI-SDAG: ; %bb.0: ; %entry
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; VI-SDAG: s_mov_b32 s7, 0xf000
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; VI-SDAG: s_mov_b32 s6, -1
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; VI-SDAG: s_mov_b32 s14, s6
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; VI-SDAG: s_mov_b32 s12, s2
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; VI-SDAG: s_mov_b32 s13, s3
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; VI-SDAG: s_mov_b32 s15, s7
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; VI-SDAG: s_mov_b32 s10, s6
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; VI-SDAG: s_mov_b32 s11, s7
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; VI-SDAG: s_mov_b32 s4, s0
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; VI-SDAG: s_movk_i32 s0, 0x4200
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; VI-SDAG: s_mov_b32 s5, s1
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; VI-SDAG: v_div_fixup_f16 v0, v0, v1, s0
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; VI-SDAG: s_endpgm
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;
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; VI-GISEL-LABEL: div_fixup_f16_imm_c:
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; VI-GISEL: ; %bb.0: ; %entry
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; VI-GISEL: s_mov_b32 s6, -1
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; VI-GISEL: s_mov_b32 s7, 0xf000
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; VI-GISEL: s_mov_b64 s[10:11], s[6:7]
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; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
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; VI-GISEL: v_mov_b32_e32 v2, 0x4200
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; VI-GISEL: v_readfirstlane_b32 s2, v0
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; VI-GISEL: v_readfirstlane_b32 s3, v1
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; VI-GISEL: v_mov_b32_e32 v0, s3
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; VI-GISEL: v_div_fixup_f16 v0, s2, v0, v2
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; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
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; VI-GISEL: s_nop 1
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; VI-GISEL: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b) {
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entry:
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%a.val = load volatile half, ptr addrspace(1) %a
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%b.val = load volatile half, ptr addrspace(1) %b
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half %b.val, half 3.0)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @div_fixup_f16_imm_a_imm_b(
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; VI-SDAG-LABEL: div_fixup_f16_imm_a_imm_b:
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; VI-SDAG: ; %bb.0: ; %entry
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; VI-SDAG: s_mov_b32 s7, 0xf000
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; VI-SDAG: s_mov_b32 s6, -1
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; VI-SDAG: s_mov_b32 s10, s6
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; VI-SDAG: s_mov_b32 s11, s7
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; VI-SDAG: s_mov_b32 s8, s2
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; VI-SDAG: s_mov_b32 s9, s3
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; VI-SDAG: s_mov_b32 s4, s0
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; VI-SDAG: s_movk_i32 s0, 0x4200
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; VI-SDAG: s_mov_b32 s5, s1
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; VI-SDAG: v_div_fixup_f16 v0, s0, s0, v0
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; VI-SDAG: s_endpgm
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;
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; VI-GISEL-LABEL: div_fixup_f16_imm_a_imm_b:
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; VI-GISEL: ; %bb.0: ; %entry
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; VI-GISEL: s_mov_b32 s6, -1
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; VI-GISEL: s_mov_b32 s7, 0xf000
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; VI-GISEL: v_mov_b32_e32 v1, 0x4200
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; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
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; VI-GISEL: v_readfirstlane_b32 s2, v0
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; VI-GISEL: v_div_fixup_f16 v0, v1, v1, s2
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; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
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; VI-GISEL: s_nop 2
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; VI-GISEL: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %c) {
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entry:
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%c.val = load volatile half, ptr addrspace(1) %c
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half 3.0, half %c.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @div_fixup_f16_imm_b_imm_c(
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; VI-SDAG-LABEL: div_fixup_f16_imm_b_imm_c:
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; VI-SDAG: ; %bb.0: ; %entry
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; VI-SDAG: s_mov_b32 s7, 0xf000
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; VI-SDAG: s_mov_b32 s6, -1
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; VI-SDAG: s_mov_b32 s10, s6
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; VI-SDAG: s_mov_b32 s11, s7
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; VI-SDAG: s_mov_b32 s8, s2
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; VI-SDAG: s_mov_b32 s9, s3
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; VI-SDAG: s_mov_b32 s4, s0
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; VI-SDAG: s_movk_i32 s0, 0x4200
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; VI-SDAG: s_mov_b32 s5, s1
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; VI-SDAG: v_div_fixup_f16 v0, v0, s0, s0
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; VI-SDAG: s_endpgm
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;
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; VI-GISEL-LABEL: div_fixup_f16_imm_b_imm_c:
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; VI-GISEL: ; %bb.0: ; %entry
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; VI-GISEL: s_mov_b32 s6, -1
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; VI-GISEL: s_mov_b32 s7, 0xf000
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; VI-GISEL: v_mov_b32_e32 v1, 0x4200
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; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
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; VI-GISEL: v_readfirstlane_b32 s2, v0
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; VI-GISEL: v_div_fixup_f16 v0, s2, v1, v1
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; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
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; VI-GISEL: s_nop 2
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; VI-GISEL: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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entry:
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%a.val = load half, ptr addrspace(1) %a
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half %a.val, half 3.0, half 3.0)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @div_fixup_f16_imm_a_imm_c(
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; VI-SDAG-LABEL: div_fixup_f16_imm_a_imm_c:
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; VI-SDAG: ; %bb.0: ; %entry
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; VI-SDAG: s_mov_b32 s7, 0xf000
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; VI-SDAG: s_mov_b32 s6, -1
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; VI-SDAG: s_mov_b32 s10, s6
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; VI-SDAG: s_mov_b32 s11, s7
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; VI-SDAG: s_mov_b32 s8, s2
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; VI-SDAG: s_mov_b32 s9, s3
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; VI-SDAG: s_mov_b32 s4, s0
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; VI-SDAG: s_movk_i32 s0, 0x4200
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; VI-SDAG: s_mov_b32 s5, s1
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; VI-SDAG: v_div_fixup_f16 v0, s0, v0, s0
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; VI-SDAG: s_endpgm
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;
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; VI-GISEL-LABEL: div_fixup_f16_imm_a_imm_c:
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; VI-GISEL: ; %bb.0: ; %entry
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; VI-GISEL: s_mov_b32 s6, -1
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; VI-GISEL: s_mov_b32 s7, 0xf000
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; VI-GISEL: v_mov_b32_e32 v1, 0x4200
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; VI-GISEL: s_mov_b64 s[4:5], s[2:3]
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; VI-GISEL: v_readfirstlane_b32 s2, v0
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; VI-GISEL: v_div_fixup_f16 v0, v1, s2, v1
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; VI-GISEL: s_mov_b64 s[2:3], s[6:7]
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; VI-GISEL: s_nop 2
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; VI-GISEL: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %b) {
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entry:
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%b.val = load half, ptr addrspace(1) %b
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%r.val = call half @llvm.amdgcn.div.fixup.f16(half 3.0, half %b.val, half 3.0)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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define half @div_fixup_f16_vgpr(half %a, half %b, half %c) {
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; VI-SDAG-LABEL: div_fixup_f16_vgpr:
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; VI-SDAG: ; %bb.0:
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; VI-SDAG: v_div_fixup_f16 v0, v0, v1, v2
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; VI-SDAG: s_setpc_b64 s[30:31]
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;
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; VI-GISEL-LABEL: div_fixup_f16_vgpr:
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; VI-GISEL: ; %bb.0:
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; VI-GISEL: v_div_fixup_f16 v0, v0, v1, v2
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; VI-GISEL: s_setpc_b64 s[30:31]
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%r = call half @llvm.amdgcn.div.fixup.f16(half %a, half %b, half %c)
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ret half %r
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}
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