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79 lines
2.8 KiB
LLVM
79 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s
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declare i32 @llvm.amdgcn.ds.add.gs.reg.rtn.i32(i32, i32 immarg)
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declare i64 @llvm.amdgcn.ds.add.gs.reg.rtn.i64(i32, i32 immarg)
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define amdgpu_gs void @test_add_32(i32 %arg) {
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; CHECK-LABEL: test_add_32:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ds_add_gs_reg_rtn v[0:1], v0 offset:16 gds
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_nop 0
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; CHECK-NEXT: s_endpgm
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%unused = call i32 @llvm.amdgcn.ds.add.gs.reg.rtn.i32(i32 %arg, i32 16)
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ret void
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}
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define amdgpu_gs void @test_add_32_use(i32 %arg, ptr addrspace(1) %out) {
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; CHECK-LABEL: test_add_32_use:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ds_add_gs_reg_rtn v[3:4], v0 offset:16 gds
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_b32 v[1:2], v3, off
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; CHECK-NEXT: s_endpgm
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%res = call i32 @llvm.amdgcn.ds.add.gs.reg.rtn.i32(i32 %arg, i32 16)
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store i32 %res, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_gs void @test_add_32_s(i32 inreg %arg, ptr addrspace(1) %out) {
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; CHECK-LABEL: test_add_32_s:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v2, s0
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; CHECK-NEXT: ds_add_gs_reg_rtn v[2:3], v2 offset:16 gds
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_b32 v[0:1], v2, off
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; CHECK-NEXT: s_endpgm
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%res = call i32 @llvm.amdgcn.ds.add.gs.reg.rtn.i32(i32 %arg, i32 16)
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store i32 %res, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_gs void @test_add_64(i32 %arg) {
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; CHECK-LABEL: test_add_64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ds_add_gs_reg_rtn v[0:1], v0 offset:32 gds
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_nop 0
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; CHECK-NEXT: s_endpgm
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%unused = call i64 @llvm.amdgcn.ds.add.gs.reg.rtn.i64(i32 %arg, i32 32)
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ret void
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}
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define amdgpu_gs void @test_add_64_use(i32 %arg, ptr addrspace(1) %out) {
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; CHECK-LABEL: test_add_64_use:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ds_add_gs_reg_rtn v[3:4], v0 offset:32 gds
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_b64 v[1:2], v[3:4], off
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; CHECK-NEXT: s_endpgm
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%res = call i64 @llvm.amdgcn.ds.add.gs.reg.rtn.i64(i32 %arg, i32 32)
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store i64 %res, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_gs void @test_add_64_s(i32 inreg %arg, ptr addrspace(1) %out) {
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; CHECK-LABEL: test_add_64_s:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v2, s0
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; CHECK-NEXT: ds_add_gs_reg_rtn v[2:3], v2 offset:32 gds
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: global_store_b64 v[0:1], v[2:3], off
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; CHECK-NEXT: s_endpgm
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%res = call i64 @llvm.amdgcn.ds.add.gs.reg.rtn.i64(i32 %arg, i32 32)
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store i64 %res, ptr addrspace(1) %out, align 8
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ret void
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}
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