derek.holloway
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51 lines
2.1 KiB
LLVM
51 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
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declare void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3))
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define void @test_ds_atomic_async_barrier_arrive_b64(ptr addrspace(3) %bar) {
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; GCN-LABEL: test_ds_atomic_async_barrier_arrive_b64:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: s_wait_alu depctr_vm_vsrc(0)
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; GCN-NEXT: ds_atomic_async_barrier_arrive_b64 v0
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; GCN-NEXT: s_wait_alu depctr_vm_vsrc(0)
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; GCN-NEXT: s_set_pc_i64 s[30:31]
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entry:
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call void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3) %bar)
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ret void
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}
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define void @test_ds_atomic_async_barrier_arrive_b64_off(ptr addrspace(3) %in) {
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; GCN-LABEL: test_ds_atomic_async_barrier_arrive_b64_off:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_wait_loadcnt_dscnt 0x0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: s_wait_alu depctr_vm_vsrc(0)
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; GCN-NEXT: ds_atomic_async_barrier_arrive_b64 v0 offset:8184
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; GCN-NEXT: s_wait_alu depctr_vm_vsrc(0)
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; GCN-NEXT: s_set_pc_i64 s[30:31]
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entry:
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%bar = getelementptr i64, ptr addrspace(3) %in, i32 1023
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call void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3) %bar)
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ret void
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}
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define amdgpu_ps void @test_ds_atomic_async_barrier_arrive_b64_s(ptr addrspace(3) inreg %bar) {
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; GCN-LABEL: test_ds_atomic_async_barrier_arrive_b64_s:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GCN-NEXT: v_nop
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: s_wait_alu depctr_vm_vsrc(0)
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; GCN-NEXT: ds_atomic_async_barrier_arrive_b64 v0
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; GCN-NEXT: s_wait_alu depctr_vm_vsrc(0)
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; GCN-NEXT: s_endpgm
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entry:
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call void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3) %bar)
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ret void
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}
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