derek.holloway
7502bf64a4
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161 lines
6.1 KiB
LLVM
161 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI-GISEL %s
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declare i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a)
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define amdgpu_kernel void @frexp_exp_f16(
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; VI-SDAG-LABEL: frexp_exp_f16:
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; VI-SDAG: ; %bb.0: ; %entry
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; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-SDAG-NEXT: s_mov_b32 s7, 0xf000
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; VI-SDAG-NEXT: s_mov_b32 s6, -1
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; VI-SDAG-NEXT: s_mov_b32 s10, s6
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; VI-SDAG-NEXT: s_mov_b32 s11, s7
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; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; VI-SDAG-NEXT: s_mov_b32 s8, s2
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; VI-SDAG-NEXT: s_mov_b32 s9, s3
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; VI-SDAG-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; VI-SDAG-NEXT: s_mov_b32 s4, s0
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; VI-SDAG-NEXT: s_mov_b32 s5, s1
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; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
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; VI-SDAG-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
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; VI-SDAG-NEXT: buffer_store_short v0, off, s[4:7], 0
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; VI-SDAG-NEXT: s_endpgm
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;
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; VI-GISEL-LABEL: frexp_exp_f16:
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; VI-GISEL: ; %bb.0: ; %entry
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; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-GISEL-NEXT: s_mov_b32 s6, -1
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; VI-GISEL-NEXT: s_mov_b32 s7, 0xf000
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; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; VI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
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; VI-GISEL-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
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; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
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; VI-GISEL-NEXT: v_frexp_exp_i16_f16_e32 v0, s2
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; VI-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7]
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; VI-GISEL-NEXT: s_nop 2
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; VI-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
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; VI-GISEL-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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entry:
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%a.val = load half, ptr addrspace(1) %a
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%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
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store i16 %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @frexp_exp_f16_sext(
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; VI-SDAG-LABEL: frexp_exp_f16_sext:
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; VI-SDAG: ; %bb.0: ; %entry
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; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-SDAG-NEXT: s_mov_b32 s7, 0xf000
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; VI-SDAG-NEXT: s_mov_b32 s6, -1
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; VI-SDAG-NEXT: s_mov_b32 s10, s6
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; VI-SDAG-NEXT: s_mov_b32 s11, s7
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; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; VI-SDAG-NEXT: s_mov_b32 s8, s2
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; VI-SDAG-NEXT: s_mov_b32 s9, s3
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; VI-SDAG-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; VI-SDAG-NEXT: s_mov_b32 s4, s0
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; VI-SDAG-NEXT: s_mov_b32 s5, s1
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; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
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; VI-SDAG-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
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; VI-SDAG-NEXT: v_bfe_i32 v0, v0, 0, 16
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; VI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; VI-SDAG-NEXT: s_endpgm
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;
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; VI-GISEL-LABEL: frexp_exp_f16_sext:
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; VI-GISEL: ; %bb.0: ; %entry
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; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-GISEL-NEXT: s_mov_b32 s6, -1
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; VI-GISEL-NEXT: s_mov_b32 s7, 0xf000
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; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; VI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
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; VI-GISEL-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
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; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
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; VI-GISEL-NEXT: v_frexp_exp_i16_f16_e32 v0, s2
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; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
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; VI-GISEL-NEXT: s_sext_i32_i16 s2, s2
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; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
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; VI-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7]
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; VI-GISEL-NEXT: s_nop 1
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; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; VI-GISEL-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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entry:
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%a.val = load half, ptr addrspace(1) %a
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%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
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%r.val.sext = sext i16 %r.val to i32
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store i32 %r.val.sext, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @frexp_exp_f16_zext(
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; VI-SDAG-LABEL: frexp_exp_f16_zext:
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; VI-SDAG: ; %bb.0: ; %entry
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; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-SDAG-NEXT: s_mov_b32 s7, 0xf000
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; VI-SDAG-NEXT: s_mov_b32 s6, -1
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; VI-SDAG-NEXT: s_mov_b32 s10, s6
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; VI-SDAG-NEXT: s_mov_b32 s11, s7
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; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; VI-SDAG-NEXT: s_mov_b32 s8, s2
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; VI-SDAG-NEXT: s_mov_b32 s9, s3
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; VI-SDAG-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; VI-SDAG-NEXT: s_mov_b32 s4, s0
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; VI-SDAG-NEXT: s_mov_b32 s5, s1
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; VI-SDAG-NEXT: s_waitcnt vmcnt(0)
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; VI-SDAG-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
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; VI-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; VI-SDAG-NEXT: s_endpgm
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;
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; VI-GISEL-LABEL: frexp_exp_f16_zext:
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; VI-GISEL: ; %bb.0: ; %entry
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; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-GISEL-NEXT: s_mov_b32 s6, -1
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; VI-GISEL-NEXT: s_mov_b32 s7, 0xf000
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; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; VI-GISEL-NEXT: s_mov_b64 s[4:5], s[2:3]
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; VI-GISEL-NEXT: buffer_load_ushort v0, off, s[4:7], 0
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; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
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; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
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; VI-GISEL-NEXT: v_frexp_exp_i16_f16_e32 v0, s2
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; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v0
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; VI-GISEL-NEXT: s_and_b32 s2, 0xffff, s2
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; VI-GISEL-NEXT: v_mov_b32_e32 v0, s2
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; VI-GISEL-NEXT: s_mov_b64 s[2:3], s[6:7]
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; VI-GISEL-NEXT: s_nop 1
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; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; VI-GISEL-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a) {
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entry:
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%a.val = load half, ptr addrspace(1) %a
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%r.val = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %a.val)
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%r.val.zext = zext i16 %r.val to i32
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store i32 %r.val.zext, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_ps i32 @v_test_frexp_exp_f16(half %src) {
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; VI-SDAG-LABEL: v_test_frexp_exp_f16:
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; VI-SDAG: ; %bb.0:
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; VI-SDAG-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
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; VI-SDAG-NEXT: v_readfirstlane_b32 s0, v0
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; VI-SDAG-NEXT: ; return to shader part epilog
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;
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; VI-GISEL-LABEL: v_test_frexp_exp_f16:
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; VI-GISEL: ; %bb.0:
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; VI-GISEL-NEXT: v_frexp_exp_i16_f16_e32 v0, v0
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; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
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; VI-GISEL-NEXT: ; return to shader part epilog
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%frexp.exp = call i16 @llvm.amdgcn.frexp.exp.i16.f16(half %src)
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%frexp.exp.zext = zext i16 %frexp.exp to i32
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ret i32 %frexp.exp.zext
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}
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