derek.holloway
7502bf64a4
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502 lines
28 KiB
LLVM
502 lines
28 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-GISEL %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-SDAG %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10_11,GFX10_11-SDAG %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-TRUE16 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-FAKE16 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-TRUE16 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12PLUS,GFX12PLUS-GISEL,GFX12PLUS-GISEL-FAKE16 %s
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define amdgpu_ps void @sample_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
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; GFX10_11-LABEL: sample_1d_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX10_11-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_1d_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX12PLUS-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) {
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; GFX10_11-LABEL: sample_2d_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX10_11-NEXT: image_sample off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_2d_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX12PLUS-NEXT: image_sample off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.2d.nortn.f32(i32 15, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_3d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %r) {
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; GFX10_11-LABEL: sample_3d_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX10_11-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_3d_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX12PLUS-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_3D
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.3d.nortn.f32(i32 15, float %s, float %t, float %r, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_cube_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %face) {
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; GFX10_11-LABEL: sample_cube_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX10_11-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_cube_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX12PLUS-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_CUBE
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.cube.nortn.f32(i32 15, float %s, float %t, float %face, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_1darray_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %slice) {
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; GFX10_11-LABEL: sample_1darray_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX10_11-NEXT: image_sample off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_1darray_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX12PLUS-NEXT: image_sample off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.1darray.nortn.f32(i32 15, float %s, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_2darray_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %slice) {
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; GFX10_11-LABEL: sample_2darray_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX10_11-NEXT: image_sample off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_2darray_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX12PLUS-NEXT: image_sample off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.2darray.nortn.f32(i32 15, float %s, float %t, float %slice, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_b_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s) {
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; GFX10_11-LABEL: sample_b_1d_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX10_11-NEXT: image_sample_b off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_b_1d_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX12PLUS-NEXT: image_sample_b off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.b.1d.nortn.f32(i32 15, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_b_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
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; GFX10_11-LABEL: sample_b_2d_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX10_11-NEXT: image_sample_b off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_b_2d_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX12PLUS-NEXT: image_sample_b off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.b.2d.nortn.f32(i32 15, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_c_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s) {
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; GFX10_11-LABEL: sample_c_1d_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX10_11-NEXT: image_sample_c off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_c_1d_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX12PLUS-NEXT: image_sample_c off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.c.1d.nortn.f32(i32 15, float %zcompare, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_c_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t) {
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; GFX10_11-LABEL: sample_c_2d_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX10_11-NEXT: image_sample_c off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_c_2d_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
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; GFX12PLUS-NEXT: image_sample_c off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.c.2d.nortn.f32(i32 15, float %zcompare, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_d_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dsdv, float %s) {
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; GFX10_11-LABEL: sample_d_1d_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: image_sample_d off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_d_1d_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: image_sample_d off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.d.1d.nortn.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_d_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {
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; GFX10_11-LABEL: sample_d_2d_nortn:
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; GFX10_11: ; %bb.0: ; %main_body
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; GFX10_11-NEXT: image_sample_d off, v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; GFX10_11-NEXT: s_endpgm
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;
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; GFX12PLUS-LABEL: sample_d_2d_nortn:
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; GFX12PLUS: ; %bb.0: ; %main_body
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; GFX12PLUS-NEXT: image_sample_d off, [v0, v1, v2, v[3:5]], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
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; GFX12PLUS-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.d.2d.nortn.f32.f32(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @sample_l_1d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %lod) {
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; GFX10_11-LABEL: sample_l_1d_nortn:
|
|
; GFX10_11: ; %bb.0: ; %main_body
|
|
; GFX10_11-NEXT: image_sample_l off, v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-NEXT: s_endpgm
|
|
;
|
|
; GFX12PLUS-LABEL: sample_l_1d_nortn:
|
|
; GFX12PLUS: ; %bb.0: ; %main_body
|
|
; GFX12PLUS-NEXT: image_sample_l off, [v0, v1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-NEXT: s_endpgm
|
|
main_body:
|
|
call void @llvm.amdgcn.image.sample.l.1d.nortn.f32(i32 15, float %s, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @sample_l_2d_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {
|
|
; GFX10_11-LABEL: sample_l_2d_nortn:
|
|
; GFX10_11: ; %bb.0: ; %main_body
|
|
; GFX10_11-NEXT: image_sample_l off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
; GFX10_11-NEXT: s_endpgm
|
|
;
|
|
; GFX12PLUS-LABEL: sample_l_2d_nortn:
|
|
; GFX12PLUS: ; %bb.0: ; %main_body
|
|
; GFX12PLUS-NEXT: image_sample_l off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D
|
|
; GFX12PLUS-NEXT: s_endpgm
|
|
main_body:
|
|
call void @llvm.amdgcn.image.sample.l.2d.nortn.f32(i32 15, float %s, float %t, float %lod, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps <4 x float> @sample_nortn_mix_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
|
|
; GFX10_11-LABEL: sample_nortn_mix_1:
|
|
; GFX10_11: ; %bb.0: ; %main_body
|
|
; GFX10_11-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX10_11-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX10_11-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10_11-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12PLUS-LABEL: sample_nortn_mix_1:
|
|
; GFX12PLUS: ; %bb.0: ; %main_body
|
|
; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX12PLUS-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12PLUS-NEXT: ; return to shader part epilog
|
|
main_body:
|
|
call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
ret <4 x float> %v
|
|
}
|
|
|
|
define amdgpu_ps <4 x float> @sample_nortn_mix_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
|
|
; GFX10_11-LABEL: sample_nortn_mix_2:
|
|
; GFX10_11: ; %bb.0: ; %main_body
|
|
; GFX10_11-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX10_11-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX10_11-NEXT: v_mov_b32_e32 v4, v0
|
|
; GFX10_11-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX10_11-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10_11-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12PLUS-LABEL: sample_nortn_mix_2:
|
|
; GFX12PLUS: ; %bb.0: ; %main_body
|
|
; GFX12PLUS-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX12PLUS-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX12PLUS-NEXT: v_mov_b32_e32 v4, v0
|
|
; GFX12PLUS-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX12PLUS-NEXT: image_sample v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12PLUS-NEXT: ; return to shader part epilog
|
|
main_body:
|
|
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
ret <4 x float> %v
|
|
}
|
|
|
|
define amdgpu_ps <4 x float> @sample_nortn_mix_3(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
|
|
; GFX10_11-SDAG-LABEL: sample_nortn_mix_3:
|
|
; GFX10_11-SDAG: ; %bb.0: ; %main_body
|
|
; GFX10_11-SDAG-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX10_11-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX10_11-SDAG-NEXT: image_sample v1, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX10_11-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-SDAG-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX10_11-SDAG-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-SDAG-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10_11-SDAG-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10_11-GISEL-LABEL: sample_nortn_mix_3:
|
|
; GFX10_11-GISEL: ; %bb.0: ; %main_body
|
|
; GFX10_11-GISEL-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX10_11-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX10_11-GISEL-NEXT: image_sample v[1:4], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX10_11-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-GISEL-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX10_11-GISEL-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10_11-GISEL-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12PLUS-SDAG-LABEL: sample_nortn_mix_3:
|
|
; GFX12PLUS-SDAG: ; %bb.0: ; %main_body
|
|
; GFX12PLUS-SDAG-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX12PLUS-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX12PLUS-SDAG-NEXT: image_sample v1, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX12PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-SDAG-NEXT: s_wait_samplecnt 0x1
|
|
; GFX12PLUS-SDAG-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-SDAG-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12PLUS-SDAG-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12PLUS-GISEL-LABEL: sample_nortn_mix_3:
|
|
; GFX12PLUS-GISEL: ; %bb.0: ; %main_body
|
|
; GFX12PLUS-GISEL-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX12PLUS-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX12PLUS-GISEL-NEXT: image_sample v[1:4], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX12PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-GISEL-NEXT: s_wait_samplecnt 0x1
|
|
; GFX12PLUS-GISEL-NEXT: image_sample v[0:3], v1, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-GISEL-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12PLUS-GISEL-NEXT: ; return to shader part epilog
|
|
main_body:
|
|
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
%v.0 = extractelement <4 x float> %v, i32 0
|
|
call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
%u = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %v.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
ret <4 x float> %u
|
|
}
|
|
|
|
define amdgpu_ps <4 x float> @sample_nortn_mix_4(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s) {
|
|
; GFX10_11-SDAG-LABEL: sample_nortn_mix_4:
|
|
; GFX10_11-SDAG: ; %bb.0: ; %main_body
|
|
; GFX10_11-SDAG-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX10_11-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX10_11-SDAG-NEXT: image_sample v4, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-SDAG-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX10_11-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-SDAG-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX10_11-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-SDAG-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX10_11-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-SDAG-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10_11-SDAG-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX10_11-GISEL-LABEL: sample_nortn_mix_4:
|
|
; GFX10_11-GISEL: ; %bb.0: ; %main_body
|
|
; GFX10_11-GISEL-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX10_11-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX10_11-GISEL-NEXT: image_sample v[4:7], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-GISEL-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX10_11-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-GISEL-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX10_11-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-GISEL-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX10_11-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX10_11-GISEL-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10_11-GISEL-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12PLUS-SDAG-LABEL: sample_nortn_mix_4:
|
|
; GFX12PLUS-SDAG: ; %bb.0: ; %main_body
|
|
; GFX12PLUS-SDAG-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX12PLUS-SDAG-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX12PLUS-SDAG-NEXT: image_sample v4, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-SDAG-NEXT: s_wait_samplecnt 0x1
|
|
; GFX12PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-SDAG-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX12PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-SDAG-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-SDAG-NEXT: s_wait_samplecnt 0x2
|
|
; GFX12PLUS-SDAG-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-SDAG-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12PLUS-SDAG-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12PLUS-GISEL-LABEL: sample_nortn_mix_4:
|
|
; GFX12PLUS-GISEL: ; %bb.0: ; %main_body
|
|
; GFX12PLUS-GISEL-NEXT: s_mov_b32 s12, exec_lo
|
|
; GFX12PLUS-GISEL-NEXT: s_wqm_b32 exec_lo, exec_lo
|
|
; GFX12PLUS-GISEL-NEXT: image_sample v[4:7], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-GISEL-NEXT: s_wait_samplecnt 0x1
|
|
; GFX12PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-GISEL-NEXT: image_sample v[0:3], v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s12
|
|
; GFX12PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-GISEL-NEXT: image_sample off, v4, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-GISEL-NEXT: s_wait_samplecnt 0x2
|
|
; GFX12PLUS-GISEL-NEXT: image_sample off, v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
|
|
; GFX12PLUS-GISEL-NEXT: s_wait_samplecnt 0x0
|
|
; GFX12PLUS-GISEL-NEXT: ; return to shader part epilog
|
|
main_body:
|
|
%v = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
%v.0 = extractelement <4 x float> %v, i32 0
|
|
%v.1 = extractelement <4 x float> %v, i32 0
|
|
%v.2 = extractelement <4 x float> %v, i32 0
|
|
%v.3 = extractelement <4 x float> %v, i32 0
|
|
call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %v.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
%u = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %v.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
%u.0 = extractelement <4 x float> %u, i32 0
|
|
call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %v.2, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
|
call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %v.3, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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call void @llvm.amdgcn.image.sample.1d.nortn.f32(i32 15, float %u.0, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret <4 x float> %u
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}
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define amdgpu_ps void @sample_d_1d_g16_nortn(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, half %dsdh, half %dsdv, float %s) {
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; GFX10_11-SDAG-LABEL: sample_d_1d_g16_nortn:
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; GFX10_11-SDAG: ; %bb.0: ; %main_body
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; GFX10_11-SDAG-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX10_11-SDAG-NEXT: s_endpgm
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;
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; GFX10_11-GISEL-LABEL: sample_d_1d_g16_nortn:
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; GFX10_11-GISEL: ; %bb.0: ; %main_body
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; GFX10_11-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GFX10_11-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
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; GFX10_11-GISEL-NEXT: v_lshl_or_b32 v0, s0, 16, v0
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; GFX10_11-GISEL-NEXT: v_lshl_or_b32 v1, s0, 16, v1
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; GFX10_11-GISEL-NEXT: image_sample_d_g16 off, v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX10_11-GISEL-NEXT: s_endpgm
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;
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; GFX12PLUS-SDAG-LABEL: sample_d_1d_g16_nortn:
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; GFX12PLUS-SDAG: ; %bb.0: ; %main_body
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; GFX12PLUS-SDAG-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX12PLUS-SDAG-NEXT: s_endpgm
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;
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; GFX12PLUS-GISEL-TRUE16-LABEL: sample_d_1d_g16_nortn:
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; GFX12PLUS-GISEL-TRUE16: ; %bb.0: ; %main_body
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; GFX12PLUS-GISEL-TRUE16-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX12PLUS-GISEL-TRUE16-NEXT: s_endpgm
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;
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; GFX12PLUS-GISEL-FAKE16-LABEL: sample_d_1d_g16_nortn:
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; GFX12PLUS-GISEL-FAKE16: ; %bb.0: ; %main_body
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; GFX12PLUS-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
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; GFX12PLUS-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
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; GFX12PLUS-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0
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; GFX12PLUS-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
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; GFX12PLUS-GISEL-FAKE16-NEXT: image_sample_d_g16 off, [v0, v1, v2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D
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; GFX12PLUS-GISEL-FAKE16-NEXT: s_endpgm
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main_body:
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call void @llvm.amdgcn.image.sample.d.1d.nortn.f16.f32(i32 15, half %dsdh, half %dsdv, float %s, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.image.sample.1d.nortn.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.2d.nortn.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.3d.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.cube.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.1darray.nortn.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.2darray.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.b.1d.nortn.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.b.2d.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.c.1d.nortn.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.c.2d.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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|
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declare void @llvm.amdgcn.image.sample.d.1d.f32.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.d.2d.f32.nortn.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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|
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declare void @llvm.amdgcn.image.sample.l.1d.nortn.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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declare void @llvm.amdgcn.image.sample.l.2d.nortn.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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|
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declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
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declare void @llvm.amdgcn.image.sample.d.1d.nortn.f16.f32(i32, half, half, float, <8 x i32>, <4 x i32>, i1, i32, i32) #0
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readonly }
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