derek.holloway
7502bf64a4
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221 lines
7.1 KiB
LLVM
221 lines
7.1 KiB
LLVM
; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
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declare float @llvm.amdgcn.rcp.f32(float) #0
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declare double @llvm.amdgcn.rcp.f64(double) #0
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declare double @llvm.amdgcn.sqrt.f64(double) #0
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declare float @llvm.amdgcn.sqrt.f32(float) #0
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declare double @llvm.sqrt.f64(double) #0
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declare float @llvm.sqrt.f32(float) #0
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; FUNC-LABEL: {{^}}rcp_undef_f32:
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; SI: v_mov_b32_e32 [[NAN:v[0-9]+]], 0x7fc00000
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; SI-NOT: [[NAN]]
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; SI: buffer_store_dword [[NAN]]
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define amdgpu_kernel void @rcp_undef_f32(ptr addrspace(1) %out) #1 {
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%rcp = call float @llvm.amdgcn.rcp.f32(float poison)
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store float %rcp, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_2_f32:
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; SI-NOT: v_rcp_f32
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; SI: v_mov_b32_e32 v{{[0-9]+}}, 0.5
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define amdgpu_kernel void @rcp_2_f32(ptr addrspace(1) %out) #1 {
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%rcp = call float @llvm.amdgcn.rcp.f32(float 2.0)
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store float %rcp, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_10_f32:
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; SI-NOT: v_rcp_f32
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; SI: v_mov_b32_e32 v{{[0-9]+}}, 0x3dcccccd
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define amdgpu_kernel void @rcp_10_f32(ptr addrspace(1) %out) #1 {
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%rcp = call float @llvm.amdgcn.rcp.f32(float 10.0)
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store float %rcp, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}safe_no_fp32_denormals_rcp_f32:
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; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
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; SI-NOT: [[RESULT]]
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; SI: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @safe_no_fp32_denormals_rcp_f32(ptr addrspace(1) %out, float %src) #1 {
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%rcp = fdiv float 1.0, %src, !fpmath !0
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store float %rcp, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}safe_f32_denormals_rcp_pat_f32:
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; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}
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; SI-NOT: [[RESULT]]
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; SI: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @safe_f32_denormals_rcp_pat_f32(ptr addrspace(1) %out, float %src) #4 {
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%rcp = fdiv afn float 1.0, %src, !fpmath !0
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store float %rcp, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}unsafe_f32_denormals_rcp_pat_f32:
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; SI: v_div_scale_f32
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define amdgpu_kernel void @unsafe_f32_denormals_rcp_pat_f32(ptr addrspace(1) %out, float %src) #3 {
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%rcp = fdiv float 1.0, %src
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store float %rcp, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}safe_rsq_rcp_pat_f32:
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; SI: v_mul_f32
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; SI: v_rsq_f32
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; SI: v_mul_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_rcp_f32
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define amdgpu_kernel void @safe_rsq_rcp_pat_f32(ptr addrspace(1) %out, float %src) #1 {
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%sqrt = call contract float @llvm.sqrt.f32(float %src)
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%rcp = call contract float @llvm.amdgcn.rcp.f32(float %sqrt)
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store float %rcp, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}safe_rsq_rcp_pat_amdgcn_sqrt_f32:
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; SI: v_sqrt_f32_e32
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; SI: v_rcp_f32_e32
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define amdgpu_kernel void @safe_rsq_rcp_pat_amdgcn_sqrt_f32(ptr addrspace(1) %out, float %src) #1 {
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%sqrt = call contract float @llvm.amdgcn.sqrt.f32(float %src)
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%rcp = call contract float @llvm.amdgcn.rcp.f32(float %sqrt)
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store float %rcp, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}safe_rsq_rcp_pat_amdgcn_sqrt_f32_nocontract:
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; SI: v_sqrt_f32_e32
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; SI: v_rcp_f32_e32
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define amdgpu_kernel void @safe_rsq_rcp_pat_amdgcn_sqrt_f32_nocontract(ptr addrspace(1) %out, float %src) #1 {
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%sqrt = call float @llvm.amdgcn.sqrt.f32(float %src)
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%rcp = call contract float @llvm.amdgcn.rcp.f32(float %sqrt)
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store float %rcp, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}unsafe_rsq_rcp_pat_f32:
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; SI: v_sqrt_f32_e32
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; SI: v_rcp_f32_e32
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define amdgpu_kernel void @unsafe_rsq_rcp_pat_f32(ptr addrspace(1) %out, float %src) #2 {
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%sqrt = call afn float @llvm.sqrt.f32(float %src)
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%rcp = call afn float @llvm.amdgcn.rcp.f32(float %sqrt)
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store float %rcp, ptr addrspace(1) %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_f64:
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; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
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; SI-NOT: [[RESULT]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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define amdgpu_kernel void @rcp_f64(ptr addrspace(1) %out, double %src) #1 {
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%rcp = call double @llvm.amdgcn.rcp.f64(double %src)
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store double %rcp, ptr addrspace(1) %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}unsafe_rcp_f64:
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; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
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; SI-NOT: [[RESULT]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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define amdgpu_kernel void @unsafe_rcp_f64(ptr addrspace(1) %out, double %src) #2 {
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%rcp = call double @llvm.amdgcn.rcp.f64(double %src)
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store double %rcp, ptr addrspace(1) %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}rcp_pat_f64:
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; SI: v_div_scale_f64
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define amdgpu_kernel void @rcp_pat_f64(ptr addrspace(1) %out, double %src) #1 {
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%rcp = fdiv double 1.0, %src
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store double %rcp, ptr addrspace(1) %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}unsafe_rcp_pat_f64:
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; SI: v_rcp_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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define amdgpu_kernel void @unsafe_rcp_pat_f64(ptr addrspace(1) %out, double %src) #2 {
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%rcp = fdiv afn double 1.0, %src
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store double %rcp, ptr addrspace(1) %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}safe_rsq_rcp_pat_f64:
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; SI-NOT: v_rsq_f64_e32
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; SI: v_rsq_f64
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; SI: v_mul_f64
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; SI: v_mul_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_rcp_f64
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define amdgpu_kernel void @safe_rsq_rcp_pat_f64(ptr addrspace(1) %out, double %src) #1 {
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%sqrt = call double @llvm.sqrt.f64(double %src)
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%rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt)
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store double %rcp, ptr addrspace(1) %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}safe_amdgcn_sqrt_rsq_rcp_pat_f64:
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; SI-NOT: v_rsq_f64_e32
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; SI: v_sqrt_f64
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; SI: v_rcp_f64
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define amdgpu_kernel void @safe_amdgcn_sqrt_rsq_rcp_pat_f64(ptr addrspace(1) %out, double %src) #1 {
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%sqrt = call double @llvm.amdgcn.sqrt.f64(double %src)
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%rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt)
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store double %rcp, ptr addrspace(1) %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}unsafe_rsq_rcp_pat_f64:
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; SI: v_rsq_f64
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; SI: v_mul_f64
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; SI: v_mul_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_fma_f64
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; SI: v_rcp_f64
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; SI: buffer_store_dwordx2
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define amdgpu_kernel void @unsafe_rsq_rcp_pat_f64(ptr addrspace(1) %out, double %src) #2 {
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%sqrt = call double @llvm.sqrt.f64(double %src)
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%rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt)
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store double %rcp, ptr addrspace(1) %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}unsafe_amdgcn_sqrt_rsq_rcp_pat_f64:
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; SI: v_sqrt_f64_e32 [[SQRT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}
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; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SQRT]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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define amdgpu_kernel void @unsafe_amdgcn_sqrt_rsq_rcp_pat_f64(ptr addrspace(1) %out, double %src) #2 {
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%sqrt = call double @llvm.amdgcn.sqrt.f64(double %src)
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%rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt)
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store double %rcp, ptr addrspace(1) %out, align 8
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind denormal_fpenv(float: preservesign) }
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attributes #2 = { nounwind denormal_fpenv(float: preservesign) }
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attributes #3 = { nounwind denormal_fpenv(float: ieee|ieee) }
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attributes #4 = { nounwind denormal_fpenv(float: ieee|ieee) }
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!0 = !{float 2.500000e+00}
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