derek.holloway
7502bf64a4
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632 lines
27 KiB
LLVM
632 lines
27 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,GFX12,GFX12-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,GFX12,GFX12-GISEL %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,GFX1250,GFX1250-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefixes=GCN,GFX1250,GFX1250-GISEL %s
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define amdgpu_ps void @prefetch_inst_sgpr_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) {
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; GFX12-LABEL: prefetch_inst_sgpr_base_sgpr_len:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: prefetch_inst_sgpr_base_sgpr_len:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
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; GFX1250-NEXT: s_endpgm
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tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_inst_sgpr_imm_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) {
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; GFX12-LABEL: prefetch_inst_sgpr_imm_base_sgpr_len:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_prefetch_inst s[0:1], 0x200, s2, 0
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: prefetch_inst_sgpr_imm_base_sgpr_len:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x200, s2, 0
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; GFX1250-NEXT: s_endpgm
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%gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
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tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %gep, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_inst_sgpr_base_imm_len(ptr addrspace(4) inreg %ptr) {
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; GFX12-LABEL: prefetch_inst_sgpr_base_imm_len:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: prefetch_inst_sgpr_base_imm_len:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
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; GFX1250-NEXT: s_endpgm
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tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 31)
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ret void
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}
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define amdgpu_ps void @prefetch_inst_sgpr_imm_base_imm_len(ptr addrspace(4) inreg %ptr) {
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; GFX12-LABEL: prefetch_inst_sgpr_imm_base_imm_len:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_prefetch_inst s[0:1], 0x200, null, 31
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: prefetch_inst_sgpr_imm_base_imm_len:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x200, null, 31
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; GFX1250-NEXT: s_endpgm
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%gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
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tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %gep, i32 31)
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ret void
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}
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define amdgpu_ps void @prefetch_inst_vgpr_base_sgpr_len(ptr addrspace(4) %ptr, i32 inreg %len) {
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; GFX12-LABEL: prefetch_inst_vgpr_base_sgpr_len:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_readfirstlane_b32 s2, v0
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; GFX12-NEXT: v_readfirstlane_b32 s3, v1
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; GFX12-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: prefetch_inst_vgpr_base_sgpr_len:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: v_readfirstlane_b32 s2, v0
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; GFX1250-NEXT: v_readfirstlane_b32 s3, v1
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; GFX1250-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
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; GFX1250-NEXT: s_endpgm
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tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_inst_vgpr_imm_base_sgpr_len(ptr addrspace(4) %ptr, i32 inreg %len) {
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; GFX12-SDAG-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len:
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; GFX12-SDAG: ; %bb.0:
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; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v0
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; GFX12-SDAG-NEXT: v_readfirstlane_b32 s3, v1
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; GFX12-SDAG-NEXT: s_prefetch_inst s[2:3], 0x200, s0, 0
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; GFX12-SDAG-NEXT: s_endpgm
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;
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; GFX12-GISEL-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len:
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; GFX12-GISEL: ; %bb.0:
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; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x200, v0
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; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
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; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v0
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; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX12-GISEL-NEXT: v_readfirstlane_b32 s3, v1
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; GFX12-GISEL-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
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; GFX12-GISEL-NEXT: s_endpgm
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;
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; GFX1250-SDAG-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v0
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v1
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; GFX1250-SDAG-NEXT: s_prefetch_inst s[2:3], 0x200, s0, 0
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: prefetch_inst_vgpr_imm_base_sgpr_len:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x200, v0
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v0
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v1
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; GFX1250-GISEL-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
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; GFX1250-GISEL-NEXT: s_endpgm
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%gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
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tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %gep, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_inst_sgpr_base_vgpr_len(ptr addrspace(4) inreg %ptr, i32 %len) {
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; GFX12-LABEL: prefetch_inst_sgpr_base_vgpr_len:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_readfirstlane_b32 s2, v0
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; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: prefetch_inst_sgpr_base_vgpr_len:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: v_readfirstlane_b32 s2, v0
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; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
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; GFX1250-NEXT: s_endpgm
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tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_inst_vgpr_base_imm_len(ptr addrspace(4) %ptr) {
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; GFX12-LABEL: prefetch_inst_vgpr_base_imm_len:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_readfirstlane_b32 s0, v0
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; GFX12-NEXT: v_readfirstlane_b32 s1, v1
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; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: prefetch_inst_vgpr_base_imm_len:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
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; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
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; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
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; GFX1250-NEXT: s_endpgm
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tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 0)
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ret void
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}
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define amdgpu_ps void @prefetch_inst_vgpr_base_vgpr_len(ptr addrspace(4) %ptr, i32 %len) {
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; GFX12-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len:
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; GFX12-SDAG: ; %bb.0:
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; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v2
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; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0
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; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v1
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; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
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; GFX12-SDAG-NEXT: s_endpgm
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;
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; GFX12-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len:
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; GFX12-GISEL: ; %bb.0:
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; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
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; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
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; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
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; GFX12-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
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; GFX12-GISEL-NEXT: s_endpgm
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;
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; GFX1250-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v0
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v1
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; GFX1250-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v1
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
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; GFX1250-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
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; GFX1250-GISEL-NEXT: s_endpgm
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tail call void @llvm.amdgcn.s.prefetch.inst.p4(ptr addrspace(4) %ptr, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_inst_sgpr_base_sgpr_len_global(ptr addrspace(1) inreg %ptr, i32 inreg %len) {
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; GFX12-LABEL: prefetch_inst_sgpr_base_sgpr_len_global:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: prefetch_inst_sgpr_base_sgpr_len_global:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
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; GFX1250-NEXT: s_endpgm
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tail call void @llvm.amdgcn.s.prefetch.inst.p1(ptr addrspace(1) %ptr, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_inst_sgpr_imm_base_sgpr_len_global(ptr addrspace(1) inreg %ptr, i32 inreg %len) {
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; GFX12-LABEL: prefetch_inst_sgpr_imm_base_sgpr_len_global:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_prefetch_inst s[0:1], 0x200, s2, 0
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; GFX12-NEXT: s_endpgm
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;
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; GFX1250-LABEL: prefetch_inst_sgpr_imm_base_sgpr_len_global:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x200, s2, 0
|
|
; GFX1250-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i32 128
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p1(ptr addrspace(1) %gep, i32 %len)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_sgpr_base_imm_len_global(ptr addrspace(1) inreg %ptr) {
|
|
; GFX12-LABEL: prefetch_inst_sgpr_base_imm_len_global:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_sgpr_base_imm_len_global:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
|
|
; GFX1250-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p1(ptr addrspace(1) %ptr, i32 31)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_sgpr_imm_base_imm_len_global(ptr addrspace(1) inreg %ptr) {
|
|
; GFX12-LABEL: prefetch_inst_sgpr_imm_base_imm_len_global:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x200, null, 31
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_sgpr_imm_base_imm_len_global:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x200, null, 31
|
|
; GFX1250-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i32 128
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p1(ptr addrspace(1) %gep, i32 31)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_vgpr_base_sgpr_len_global(ptr addrspace(1) %ptr, i32 inreg %len) {
|
|
; GFX12-LABEL: prefetch_inst_vgpr_base_sgpr_len_global:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_readfirstlane_b32 s2, v0
|
|
; GFX12-NEXT: v_readfirstlane_b32 s3, v1
|
|
; GFX12-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_vgpr_base_sgpr_len_global:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s2, v0
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s3, v1
|
|
; GFX1250-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
|
|
; GFX1250-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p1(ptr addrspace(1) %ptr, i32 %len)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_vgpr_base_imm_len_global(ptr addrspace(1) %ptr) {
|
|
; GFX12-LABEL: prefetch_inst_vgpr_base_imm_len_global:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX12-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_vgpr_base_imm_len_global:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
|
|
; GFX1250-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p1(ptr addrspace(1) %ptr, i32 0)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_sgpr_base_vgpr_len_global(ptr addrspace(1) inreg %ptr, i32 %len) {
|
|
; GFX12-LABEL: prefetch_inst_sgpr_base_vgpr_len_global:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_readfirstlane_b32 s2, v0
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_sgpr_base_vgpr_len_global:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s2, v0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX1250-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p1(ptr addrspace(1) %ptr, i32 %len)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_vgpr_base_vgpr_len_global(ptr addrspace(1) %ptr, i32 %len) {
|
|
; GFX12-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len_global:
|
|
; GFX12-SDAG: ; %bb.0:
|
|
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v2
|
|
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX12-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX12-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len_global:
|
|
; GFX12-GISEL: ; %bb.0:
|
|
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
|
|
; GFX12-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX12-GISEL-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len_global:
|
|
; GFX1250-SDAG: ; %bb.0:
|
|
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-SDAG-NEXT: v_nop
|
|
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX1250-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX1250-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len_global:
|
|
; GFX1250-GISEL: ; %bb.0:
|
|
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-GISEL-NEXT: v_nop
|
|
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
|
|
; GFX1250-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX1250-GISEL-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p1(ptr addrspace(1) %ptr, i32 %len)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_sgpr_base_sgpr_len_flat(ptr inreg %ptr, i32 inreg %len) {
|
|
; GFX12-LABEL: prefetch_inst_sgpr_base_sgpr_len_flat:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_sgpr_base_sgpr_len_flat:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX1250-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr %ptr, i32 %len)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_sgpr_imm_base_sgpr_len_flat(ptr inreg %ptr, i32 inreg %len) {
|
|
; GFX12-LABEL: prefetch_inst_sgpr_imm_base_sgpr_len_flat:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x200, s2, 0
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_sgpr_imm_base_sgpr_len_flat:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x200, s2, 0
|
|
; GFX1250-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr %ptr, i32 128
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr %gep, i32 %len)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_sgpr_base_imm_len_flat(ptr inreg %ptr) {
|
|
; GFX12-LABEL: prefetch_inst_sgpr_base_imm_len_flat:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_sgpr_base_imm_len_flat:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
|
|
; GFX1250-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr %ptr, i32 31)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_sgpr_imm_base_imm_len_flat(ptr inreg %ptr) {
|
|
; GFX12-LABEL: prefetch_inst_sgpr_imm_base_imm_len_flat:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x200, null, 31
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_sgpr_imm_base_imm_len_flat:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x200, null, 31
|
|
; GFX1250-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr %ptr, i32 128
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr %gep, i32 31)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_vgpr_base_sgpr_len_flat(ptr %ptr, i32 inreg %len) {
|
|
; GFX12-LABEL: prefetch_inst_vgpr_base_sgpr_len_flat:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_readfirstlane_b32 s2, v0
|
|
; GFX12-NEXT: v_readfirstlane_b32 s3, v1
|
|
; GFX12-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_vgpr_base_sgpr_len_flat:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s2, v0
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s3, v1
|
|
; GFX1250-NEXT: s_prefetch_inst s[2:3], 0x0, s0, 0
|
|
; GFX1250-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr %ptr, i32 %len)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_vgpr_base_imm_len_flat(ptr %ptr) {
|
|
; GFX12-LABEL: prefetch_inst_vgpr_base_imm_len_flat:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX12-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_vgpr_base_imm_len_flat:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 0
|
|
; GFX1250-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr %ptr, i32 0)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_sgpr_base_vgpr_len_flat(ptr inreg %ptr, i32 %len) {
|
|
; GFX12-LABEL: prefetch_inst_sgpr_base_vgpr_len_flat:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_readfirstlane_b32 s2, v0
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_sgpr_base_vgpr_len_flat:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_readfirstlane_b32 s2, v0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX1250-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr %ptr, i32 %len)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_vgpr_base_vgpr_len_flat(ptr %ptr, i32 %len) {
|
|
; GFX12-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len_flat:
|
|
; GFX12-SDAG: ; %bb.0:
|
|
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s2, v2
|
|
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX12-SDAG-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX12-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX12-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX12-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len_flat:
|
|
; GFX12-GISEL: ; %bb.0:
|
|
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX12-GISEL-NEXT: v_readfirstlane_b32 s2, v2
|
|
; GFX12-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX12-GISEL-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-SDAG-LABEL: prefetch_inst_vgpr_base_vgpr_len_flat:
|
|
; GFX1250-SDAG: ; %bb.0:
|
|
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-SDAG-NEXT: v_nop
|
|
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX1250-SDAG-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX1250-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-GISEL-LABEL: prefetch_inst_vgpr_base_vgpr_len_flat:
|
|
; GFX1250-GISEL: ; %bb.0:
|
|
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-GISEL-NEXT: v_nop
|
|
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v0
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v1
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
|
|
; GFX1250-GISEL-NEXT: s_prefetch_inst s[0:1], 0x0, s2, 0
|
|
; GFX1250-GISEL-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr %ptr, i32 %len)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_function_target() {
|
|
; GFX12-LABEL: prefetch_inst_function_target:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_getpc_b64 s[0:1]
|
|
; GFX12-NEXT: s_sext_i32_i16 s1, s1
|
|
; GFX12-NEXT: s_add_co_u32 s0, s0, target@gotpcrel32@lo+8
|
|
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, target@gotpcrel32@hi+16
|
|
; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_function_target:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: s_get_pc_i64 s[0:1]
|
|
; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], target@gotpcrel+4
|
|
; GFX1250-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 nv
|
|
; GFX1250-NEXT: s_wait_kmcnt 0x0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
|
|
; GFX1250-NEXT: s_endpgm
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr @target, i32 31)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @prefetch_inst_blockaddress() {
|
|
; GFX12-LABEL: prefetch_inst_blockaddress:
|
|
; GFX12: ; %bb.0: ; %entry
|
|
; GFX12-NEXT: s_getpc_b64 s[0:1]
|
|
; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], .Ltmp0
|
|
; GFX12-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
|
|
; GFX12-NEXT: .Ltmp0: ; Block address taken
|
|
; GFX12-NEXT: ; %bb.1: ; %bb
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: prefetch_inst_blockaddress:
|
|
; GFX1250: ; %bb.0: ; %entry
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: s_get_pc_i64 s[0:1]
|
|
; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], .Ltmp0
|
|
; GFX1250-NEXT: s_prefetch_inst s[0:1], 0x0, null, 31
|
|
; GFX1250-NEXT: .Ltmp0: ; Block address taken
|
|
; GFX1250-NEXT: ; %bb.1: ; %bb
|
|
; GFX1250-NEXT: s_endpgm
|
|
entry:
|
|
tail call void @llvm.amdgcn.s.prefetch.inst.p0(ptr blockaddress(@prefetch_inst_blockaddress, %bb), i32 31)
|
|
br label %bb
|
|
bb:
|
|
ret void
|
|
}
|
|
|
|
declare amdgpu_ps void @target()
|
|
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
|
; GCN: {{.*}}
|