derek.holloway
7502bf64a4
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49 lines
2.2 KiB
LLVM
49 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck %s --check-prefixes=GCN,GFX906
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1031 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s --check-prefixes=GFX11
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declare i32 @llvm.amdgcn.sdot4(i32 %a, i32 %b, i32 %c, i1 %clamp)
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; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4_clamp
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; GFX906: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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; GFX10: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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; GFX11: v_dot4_i32_iu8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} neg_lo:[1,1,0] clamp{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_sdot4_clamp(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load <4 x i8>, ptr addrspace(1) %a
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%b.val = load <4 x i8>, ptr addrspace(1) %b
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%a.val.cast = bitcast <4 x i8> %a.val to i32
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%b.val.cast = bitcast <4 x i8> %b.val to i32
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%c.val = load i32, ptr addrspace(1) %c
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%r.val = call i32 @llvm.amdgcn.sdot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 1)
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store i32 %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot4_no_clamp
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; GFX906: v_dot4_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GFX10: v_dot4c_i32_i8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GF11: v_dot4_i32_iu8 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}} neg_lo:[1,1,0]{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_sdot4_no_clamp(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load <4 x i8>, ptr addrspace(1) %a
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%b.val = load <4 x i8>, ptr addrspace(1) %b
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%a.val.cast = bitcast <4 x i8> %a.val to i32
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%b.val.cast = bitcast <4 x i8> %b.val to i32
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%c.val = load i32, ptr addrspace(1) %c
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%r.val = call i32 @llvm.amdgcn.sdot4(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 0)
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store i32 %r.val, ptr addrspace(1) %r
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ret void
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}
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