derek.holloway
7502bf64a4
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302 lines
16 KiB
LLVM
302 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
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; %D4 should be zero-initialized for gfx1250, which only supports 4 groups of tensor descriptor
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declare void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 %cpol)
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declare void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 %cpol)
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define amdgpu_ps void @tensor_load_to_lds_d4(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) {
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; GFX1250-LABEL: tensor_load_to_lds_d4:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11], s[12:15], s[16:19]
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; GFX1250-NEXT: s_endpgm
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call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> zeroinitializer, i32 0)
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ret void
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}
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define amdgpu_ps void @tensor_load_to_lds_d4_vector(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3) {
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; GFX1250-SDAG-LABEL: tensor_load_to_lds_d4_vector:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v7
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s4, v8
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v0
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v1
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s10, v2
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s11, v3
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s5, v9
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s6, v10
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s7, v11
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s12, v12
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s13, v13
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s14, v14
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s15, v15
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s16, v16
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s17, v17
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s18, v18
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s19, v19
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; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-SDAG-NEXT: tensor_load_to_lds s[8:11], s[0:7], s[12:15], s[16:19]
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: tensor_load_to_lds_d4_vector:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v3
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v4
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v5
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v6
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v7
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v8
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v9
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v10
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v11
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s12, v12
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s13, v13
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s14, v14
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s15, v15
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s16, v16
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s17, v17
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s18, v18
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s19, v19
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: tensor_load_to_lds s[8:11], s[0:7], s[12:15], s[16:19]
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; GFX1250-GISEL-NEXT: s_endpgm
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call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> zeroinitializer, i32 0)
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ret void
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}
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define amdgpu_ps void @tensor_load_to_lds_d2(<4 x i32> inreg %D0, <8 x i32> inreg %D1) {
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; GFX1250-LABEL: tensor_load_to_lds_d2:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11] th:TH_LOAD_BYPASS scope:SCOPE_SYS
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; GFX1250-NEXT: s_endpgm
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call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 27)
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ret void
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}
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define amdgpu_ps void @tensor_load_to_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1) {
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; GFX1250-SDAG-LABEL: tensor_load_to_lds_d2_vector:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v0
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v1
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s10, v2
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s11, v3
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v7
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s4, v8
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s5, v9
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s6, v10
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s7, v11
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; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-SDAG-NEXT: tensor_load_to_lds s[8:11], s[0:7] th:TH_LOAD_BYPASS scope:SCOPE_SYS
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: tensor_load_to_lds_d2_vector:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v3
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v4
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v5
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v6
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v7
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v8
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v9
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v10
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v11
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: tensor_load_to_lds s[8:11], s[0:7] th:TH_LOAD_BYPASS scope:SCOPE_SYS
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; GFX1250-GISEL-NEXT: s_endpgm
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call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 27)
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ret void
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}
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define amdgpu_ps void @tensor_store_from_lds_d4(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3) {
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; GFX1250-LABEL: tensor_store_from_lds_d4:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
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; GFX1250-NEXT: s_endpgm
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call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> zeroinitializer, i32 22)
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ret void
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}
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define amdgpu_ps void @tensor_store_from_lds_d4_vector(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3) {
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; GFX1250-SDAG-LABEL: tensor_store_from_lds_d4_vector:
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; GFX1250-SDAG: ; %bb.0:
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; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-SDAG-NEXT: v_nop
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; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v7
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s4, v8
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v0
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v1
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s10, v2
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s11, v3
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s5, v9
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s6, v10
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s7, v11
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s12, v12
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s13, v13
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s14, v14
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s15, v15
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s16, v16
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s17, v17
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s18, v18
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; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s19, v19
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; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-SDAG-NEXT: tensor_store_from_lds s[8:11], s[0:7], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
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; GFX1250-SDAG-NEXT: s_endpgm
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;
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; GFX1250-GISEL-LABEL: tensor_store_from_lds_d4_vector:
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; GFX1250-GISEL: ; %bb.0:
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; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-GISEL-NEXT: v_nop
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; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v3
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v4
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v5
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v6
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v7
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v8
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v9
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v10
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v11
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s12, v12
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s13, v13
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s14, v14
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s15, v15
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s16, v16
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s17, v17
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s18, v18
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; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s19, v19
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; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX1250-GISEL-NEXT: tensor_store_from_lds s[8:11], s[0:7], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
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; GFX1250-GISEL-NEXT: s_endpgm
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call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> zeroinitializer, i32 22)
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ret void
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}
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define amdgpu_ps void @tensor_store_from_lds_d2(<4 x i32> inreg %D0, <8 x i32> inreg %D1) {
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; GFX1250-LABEL: tensor_store_from_lds_d2:
|
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; GFX1250: ; %bb.0:
|
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11]
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; GFX1250-NEXT: s_endpgm
|
|
call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @tensor_store_from_lds_d2_vector(<4 x i32> %D0, <8 x i32> %D1) {
|
|
; GFX1250-SDAG-LABEL: tensor_store_from_lds_d2_vector:
|
|
; GFX1250-SDAG: ; %bb.0:
|
|
; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-SDAG-NEXT: v_nop
|
|
; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s8, v0
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s9, v1
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s10, v2
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s11, v3
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s1, v5
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v6
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s3, v7
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s4, v8
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s5, v9
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s6, v10
|
|
; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s7, v11
|
|
; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX1250-SDAG-NEXT: tensor_store_from_lds s[8:11], s[0:7]
|
|
; GFX1250-SDAG-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-GISEL-LABEL: tensor_store_from_lds_d2_vector:
|
|
; GFX1250-GISEL: ; %bb.0:
|
|
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-GISEL-NEXT: v_nop
|
|
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v0
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v1
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v2
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v3
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v4
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v5
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v6
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v7
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v8
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v9
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v10
|
|
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v11
|
|
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX1250-GISEL-NEXT: tensor_store_from_lds s[8:11], s[0:7]
|
|
; GFX1250-GISEL-NEXT: s_endpgm
|
|
call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 0)
|
|
ret void
|
|
}
|
|
|
|
;=======================================================================
|
|
; It is fine to pass 5 arguments as tensor descriptor, but the fifth one
|
|
; will be ignored silently by the CodeGen for gfx1250, which only
|
|
; supports D# up to 4 groups.
|
|
;========================================================================
|
|
|
|
define amdgpu_ps void @tensor_load_to_lds_d5(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3, <8 x i32> inreg %D4) {
|
|
; GFX1250-LABEL: tensor_load_to_lds_d5:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: tensor_load_to_lds s[0:3], s[4:11], s[12:15], s[16:19]
|
|
; GFX1250-NEXT: s_endpgm
|
|
call void @llvm.amdgcn.tensor.load.to.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 0)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @tensor_store_from_lds_d5(<4 x i32> inreg %D0, <8 x i32> inreg %D1, <4 x i32> inreg %D2, <4 x i32> inreg %D3, <8 x i32> inreg %D4) {
|
|
; GFX1250-LABEL: tensor_store_from_lds_d5:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: tensor_store_from_lds s[0:3], s[4:11], s[12:15], s[16:19] th:TH_STORE_NT_HT scope:SCOPE_DEV
|
|
; GFX1250-NEXT: s_endpgm
|
|
call void @llvm.amdgcn.tensor.store.from.lds(<4 x i32> %D0, <8 x i32> %D1, <4 x i32> %D2, <4 x i32> %D3, <8 x i32> %D4, i32 22)
|
|
ret void
|
|
}
|