derek.holloway
7502bf64a4
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178 lines
9.8 KiB
LLVM
178 lines
9.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes='amdgpu-lower-intrinsics,function(amdgpu-annotate-uniform)' -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -codegen-opt-level=1 -mattr=+wavefrontsize32 < %s | FileCheck --check-prefix=NOCLOBBER %s
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; RUN: opt -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -codegen-opt-level=1 -mattr=+wavefrontsize32 < %s | FileCheck --check-prefix=GFX11 %s
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; RUN: opt -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -codegen-opt-level=1 -mattr=+wavefrontsize32 < %s | FileCheck --check-prefix=GFX12 %s
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; Verify that amdgpu-lower-intrinsics preserves metadata when lowering
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; barrier intrinsics to other barrier intrinsics or wave_barrier.
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; The original noclobber motivation test: without metadata preservation,
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; MemorySSA can no longer see past the barrier, walks further, and may
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; reach an unrelated side-effecting def that falsely blocks
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; !amdgpu.noclobber on a later global load.
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define amdgpu_kernel void @noclobber_after_barrier_lowering(ptr addrspace(1) %arg, ptr addrspace(3) %lds) "amdgpu-flat-work-group-size"="1,32" {
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; NOCLOBBER-LABEL: @noclobber_after_barrier_lowering(
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; NOCLOBBER-NEXT: bb:
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; NOCLOBBER-NEXT: store i32 99, ptr addrspace(3) [[LDS:%.*]], align 4, !tbaa [[TBAA0:![0-9]+]], !alias.scope [[META4:![0-9]+]], !noalias [[META7:![0-9]+]]
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; NOCLOBBER-NEXT: call void @llvm.amdgcn.wave.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; NOCLOBBER-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG:%.*]], i64 1, !amdgpu.uniform [[META9:![0-9]+]]
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; NOCLOBBER-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !alias.scope [[META7]], !noalias [[META4]], !amdgpu.noclobber [[META9]]
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; NOCLOBBER-NEXT: store i32 [[VAL]], ptr addrspace(1) [[ARG]], align 4
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; NOCLOBBER-NEXT: ret void
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;
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; GFX11-LABEL: @noclobber_after_barrier_lowering(
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; GFX11-NEXT: bb:
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; GFX11-NEXT: store i32 99, ptr addrspace(3) [[LDS:%.*]], align 4, !tbaa [[TBAA0:![0-9]+]], !alias.scope [[META4:![0-9]+]], !noalias [[META7:![0-9]+]]
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; GFX11-NEXT: call void @llvm.amdgcn.wave.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX11-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG:%.*]], i64 1
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; GFX11-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !alias.scope [[META7]], !noalias [[META4]]
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; GFX11-NEXT: store i32 [[VAL]], ptr addrspace(1) [[ARG]], align 4
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; GFX11-NEXT: ret void
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;
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; GFX12-LABEL: @noclobber_after_barrier_lowering(
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; GFX12-NEXT: bb:
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; GFX12-NEXT: store i32 99, ptr addrspace(3) [[LDS:%.*]], align 4, !tbaa [[TBAA0:![0-9]+]], !alias.scope [[META4:![0-9]+]], !noalias [[META7:![0-9]+]]
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; GFX12-NEXT: call void @llvm.amdgcn.wave.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG:%.*]], i64 1
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; GFX12-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !alias.scope [[META7]], !noalias [[META4]]
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; GFX12-NEXT: store i32 [[VAL]], ptr addrspace(1) [[ARG]], align 4
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; GFX12-NEXT: ret void
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;
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bb:
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store i32 99, ptr addrspace(3) %lds, align 4, !alias.scope !4, !noalias !1, !tbaa !5
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tail call void @llvm.amdgcn.s.barrier(), !noalias !1, !alias.scope !4, !tbaa !5
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%gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 1
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%val = load i32, ptr addrspace(1) %gep, align 4, !alias.scope !1, !noalias !4
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store i32 %val, ptr addrspace(1) %arg, align 4
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ret void
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}
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; Single-wave s_barrier -> wave_barrier
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define amdgpu_kernel void @barrier_single_wave(ptr addrspace(1) %arg) "amdgpu-flat-work-group-size"="1,32" {
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; NOCLOBBER-LABEL: @barrier_single_wave(
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; NOCLOBBER-NEXT: bb:
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; NOCLOBBER-NEXT: call void @llvm.amdgcn.wave.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; NOCLOBBER-NEXT: ret void
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;
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; GFX11-LABEL: @barrier_single_wave(
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; GFX11-NEXT: bb:
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; GFX11-NEXT: call void @llvm.amdgcn.wave.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX11-NEXT: ret void
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;
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; GFX12-LABEL: @barrier_single_wave(
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; GFX12-NEXT: bb:
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; GFX12-NEXT: call void @llvm.amdgcn.wave.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: ret void
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;
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bb:
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tail call void @llvm.amdgcn.s.barrier(), !noalias !1, !alias.scope !4, !tbaa !5
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ret void
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}
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; Multi-wave s_barrier -> s_barrier_signal + s_barrier_wait (GFX12 split barriers)
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define amdgpu_kernel void @barrier_multi_wave(ptr addrspace(1) %arg) {
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; NOCLOBBER-LABEL: @barrier_multi_wave(
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; NOCLOBBER-NEXT: bb:
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; NOCLOBBER-NEXT: tail call void @llvm.amdgcn.s.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; NOCLOBBER-NEXT: ret void
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;
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; GFX11-LABEL: @barrier_multi_wave(
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; GFX11-NEXT: bb:
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; GFX11-NEXT: tail call void @llvm.amdgcn.s.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX11-NEXT: ret void
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;
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; GFX12-LABEL: @barrier_multi_wave(
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; GFX12-NEXT: bb:
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; GFX12-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: ret void
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;
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bb:
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tail call void @llvm.amdgcn.s.barrier(), !noalias !1, !alias.scope !4, !tbaa !5
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ret void
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}
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; Single-wave s_cluster_barrier -> wave_barrier
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define amdgpu_kernel void @cluster_barrier_single_wave(ptr addrspace(1) %arg) "amdgpu-flat-work-group-size"="1,32" {
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; NOCLOBBER-LABEL: @cluster_barrier_single_wave(
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; NOCLOBBER-NEXT: bb:
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; NOCLOBBER-NEXT: call void @llvm.amdgcn.wave.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; NOCLOBBER-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; NOCLOBBER-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; NOCLOBBER-NEXT: ret void
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;
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; GFX11-LABEL: @cluster_barrier_single_wave(
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; GFX11-NEXT: bb:
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; GFX11-NEXT: call void @llvm.amdgcn.wave.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX11-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX11-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX11-NEXT: ret void
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;
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; GFX12-LABEL: @cluster_barrier_single_wave(
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; GFX12-NEXT: bb:
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; GFX12-NEXT: call void @llvm.amdgcn.wave.barrier(), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: ret void
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;
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bb:
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tail call void @llvm.amdgcn.s.cluster.barrier(), !noalias !1, !alias.scope !4, !tbaa !5
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ret void
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}
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; Multi-wave s_cluster_barrier -> signal_isfirst + wait + signal(cluster) + wait(cluster)
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define amdgpu_kernel void @cluster_barrier_multi_wave(ptr addrspace(1) %arg) {
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; NOCLOBBER-LABEL: @cluster_barrier_multi_wave(
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; NOCLOBBER-NEXT: bb:
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; NOCLOBBER-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; NOCLOBBER-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; NOCLOBBER-NEXT: br i1 [[TMP0]], label [[TMP1:%.*]], label [[TMP2:%.*]], !amdgpu.uniform [[META9]]
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; NOCLOBBER: 1:
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; NOCLOBBER-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; NOCLOBBER-NEXT: br label [[TMP2]]
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; NOCLOBBER: 2:
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; NOCLOBBER-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; NOCLOBBER-NEXT: ret void
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;
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; GFX11-LABEL: @cluster_barrier_multi_wave(
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; GFX11-NEXT: bb:
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; GFX11-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX11-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX11-NEXT: br i1 [[TMP0]], label [[TMP1:%.*]], label [[TMP2:%.*]]
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; GFX11: 1:
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; GFX11-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX11-NEXT: br label [[TMP2]]
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; GFX11: 2:
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; GFX11-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX11-NEXT: ret void
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;
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; GFX12-LABEL: @cluster_barrier_multi_wave(
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; GFX12-NEXT: bb:
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; GFX12-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: br i1 [[TMP0]], label [[TMP1:%.*]], label [[TMP2:%.*]]
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; GFX12: 1:
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; GFX12-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: br label [[TMP2]]
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; GFX12: 2:
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; GFX12-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -3), !tbaa [[TBAA0]], !alias.scope [[META4]], !noalias [[META7]]
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; GFX12-NEXT: ret void
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;
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bb:
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tail call void @llvm.amdgcn.s.cluster.barrier(), !noalias !1, !alias.scope !4, !tbaa !5
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ret void
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}
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declare void @llvm.amdgcn.s.barrier()
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declare void @llvm.amdgcn.s.cluster.barrier()
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!0 = distinct !{!0, !"domain"}
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!2 = distinct !{!2, !0, !"global_scope"}
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!3 = distinct !{!3, !0, !"lds_scope"}
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!1 = !{!2}
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!4 = !{!3}
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!5 = !{!6, !6, i64 0}
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!6 = !{!"int", !7, i64 0}
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!7 = !{!"omnipotent char", !8, i64 0}
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!8 = !{!"Simple C/C++ TBAA"}
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