derek.holloway
7502bf64a4
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47 lines
1.7 KiB
LLVM
47 lines
1.7 KiB
LLVM
; RUN: opt -S -passes=amdgpu-late-codegenprepare \
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; RUN: -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s | FileCheck %s
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; Goal: With a loop-header PHI in illegal vector type and a same-BB
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; non-lookthrough user (vector add) in the header, LRO should still coerce
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; the PHI to i32 because a profitable sink (store) exists across BB.
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define amdgpu_kernel void @phi_samebb_nonlookthrough_store(
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ptr addrspace(1) %out, <4 x i8> %v, i1 %exit) {
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; CHECK-LABEL: @phi_samebb_nonlookthrough_store(
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entry:
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br label %loop
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loop: ; preds = %entry, %loop
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; Loop-carried PHI in illegal vector type.
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%acc = phi <4 x i8> [ zeroinitializer, %entry ], [ %acc.next, %loop ]
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; Same-BB non-lookthrough use in header.
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%acc.next = add <4 x i8> %acc, %v
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; Make it a real loop: either iterate or exit to the sink block.
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br i1 %exit, label %store, label %loop
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store: ; preds = %loop
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; The across-BB sink: storing the PHI coerced to i32.
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%acc.bc = bitcast <4 x i8> %acc to i32
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store i32 %acc.bc, ptr addrspace(1) %out, align 4
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ret void
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}
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; After AMDGPULateCodeGenPrepare we expect:
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; - PHI is coerced to i32
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; - A header bitcast materializes for the add
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; This proves the same-BB non-lookthrough user (add) did not get pruned
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; when the def is a PHI.
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; CHECK: loop:
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; CHECK: %[[ACC_TC:[^ ]+]] = phi i32
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; CHECK: %[[ACC_TC_BC:[^ ]+]] = bitcast i32 %[[ACC_TC]] to <4 x i8>
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; CHECK: %[[ACC_NEXT:[^ ]+]] = add <4 x i8> %[[ACC_TC_BC]], %v
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; CHECK: br i1 %exit, label %store, label %loop
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; CHECK: store:
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; CHECK: %[[ACC_TC_BC2:[^ ]+]] = bitcast i32 %[[ACC_TC]] to <4 x i8>
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; CHECK: %[[ST_I32:[^ ]+]] = bitcast <4 x i8> %[[ACC_TC_BC2]] to i32
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; CHECK: store i32 %[[ST_I32]],
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