derek.holloway
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112 lines
5.2 KiB
LLVM
112 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="-wavefrontsize32,+wavefrontsize64" -o - < %s | FileCheck -check-prefixes=SDAG-W64 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="-wavefrontsize32,+wavefrontsize64" -o - < %s | FileCheck -check-prefixes=GISEL-W64 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="+wavefrontsize32,-wavefrontsize64" -o - < %s | FileCheck -check-prefixes=SDAG-W32 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="+wavefrontsize32,-wavefrontsize64" -o - < %s | FileCheck -check-prefixes=GISEL-W32 %s
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; Use ballot for easy access to lanemask
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define amdgpu_ps i64 @test_nor(i64 inreg %a, i64 inreg %b) {
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; SDAG-W64-LABEL: test_nor:
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; SDAG-W64: ; %bb.0:
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; SDAG-W64-NEXT: s_nor_b64 s[0:1], s[0:1], s[2:3]
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; SDAG-W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; SDAG-W64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
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; SDAG-W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0
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; SDAG-W64-NEXT: s_waitcnt_depctr depctr_va_sdst(0)
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; SDAG-W64-NEXT: ; return to shader part epilog
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;
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; GISEL-W64-LABEL: test_nor:
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; GISEL-W64: ; %bb.0:
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; GISEL-W64-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
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; GISEL-W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GISEL-W64-NEXT: s_xor_b64 s[0:1], s[0:1], exec
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; GISEL-W64-NEXT: s_and_b64 s[0:1], s[0:1], exec
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; GISEL-W64-NEXT: ; return to shader part epilog
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;
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; SDAG-W32-LABEL: test_nor:
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; SDAG-W32: ; %bb.0:
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; SDAG-W32-NEXT: s_nor_b32 s0, s0, s2
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; SDAG-W32-NEXT: s_mov_b32 s1, 0
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; SDAG-W32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
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; SDAG-W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; SDAG-W32-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
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; SDAG-W32-NEXT: ; return to shader part epilog
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;
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; GISEL-W32-LABEL: test_nor:
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; GISEL-W32: ; %bb.0:
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; GISEL-W32-NEXT: s_or_b32 s0, s0, s2
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; GISEL-W32-NEXT: s_mov_b32 s1, 0
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; GISEL-W32-NEXT: s_xor_b32 s0, s0, exec_lo
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; GISEL-W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GISEL-W32-NEXT: s_and_b32 s0, s0, exec_lo
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; GISEL-W32-NEXT: ; return to shader part epilog
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%a.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %a)
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%b.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %b)
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%or = or i1 %a.lanemask, %b.lanemask
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%xor = xor i1 %or, true
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%r = call i64 @llvm.amdgcn.ballot.i64(i1 %xor)
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ret i64 %r
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}
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define amdgpu_ps i64 @test_or_two_uses(i64 inreg %a, i64 inreg %b) {
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; SDAG-W64-LABEL: test_or_two_uses:
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; SDAG-W64: ; %bb.0:
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; SDAG-W64-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
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; SDAG-W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
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; SDAG-W64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
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; SDAG-W64-NEXT: s_xor_b64 s[0:1], s[0:1], -1
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; SDAG-W64-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)
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; SDAG-W64-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
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; SDAG-W64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
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; SDAG-W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; SDAG-W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
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; SDAG-W64-NEXT: s_waitcnt_depctr depctr_va_sdst(0)
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; SDAG-W64-NEXT: s_and_b64 s[0:1], s[0:1], vcc
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; SDAG-W64-NEXT: ; return to shader part epilog
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;
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; GISEL-W64-LABEL: test_or_two_uses:
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; GISEL-W64: ; %bb.0:
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; GISEL-W64-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
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; GISEL-W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
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; GISEL-W64-NEXT: s_xor_b64 s[2:3], s[0:1], exec
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; GISEL-W64-NEXT: s_and_b64 s[0:1], s[0:1], exec
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; GISEL-W64-NEXT: s_and_b64 s[2:3], s[2:3], exec
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; GISEL-W64-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
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; GISEL-W64-NEXT: ; return to shader part epilog
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;
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; SDAG-W32-LABEL: test_or_two_uses:
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; SDAG-W32: ; %bb.0:
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; SDAG-W32-NEXT: s_or_b32 s0, s0, s2
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; SDAG-W32-NEXT: s_mov_b32 s3, 0
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; SDAG-W32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
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; SDAG-W32-NEXT: s_xor_b32 s0, s0, -1
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; SDAG-W32-NEXT: s_mov_b32 s1, s3
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; SDAG-W32-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
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; SDAG-W32-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; SDAG-W32-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
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; SDAG-W32-NEXT: v_cmp_ne_u32_e64 s2, 0, v1
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; SDAG-W32-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
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; SDAG-W32-NEXT: ; return to shader part epilog
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;
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; GISEL-W32-LABEL: test_or_two_uses:
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; GISEL-W32: ; %bb.0:
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; GISEL-W32-NEXT: s_or_b32 s2, s0, s2
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; GISEL-W32-NEXT: s_mov_b32 s1, 0
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; GISEL-W32-NEXT: s_xor_b32 s0, s2, exec_lo
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; GISEL-W32-NEXT: s_and_b32 s2, s2, exec_lo
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; GISEL-W32-NEXT: s_and_b32 s0, s0, exec_lo
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; GISEL-W32-NEXT: s_mov_b32 s3, s1
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; GISEL-W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GISEL-W32-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]
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; GISEL-W32-NEXT: ; return to shader part epilog
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%a.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %a)
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%b.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %b)
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%or = or i1 %a.lanemask, %b.lanemask
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%xor = xor i1 %or, true
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%r0 = call i64 @llvm.amdgcn.ballot.i64(i1 %xor)
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%r1 = call i64 @llvm.amdgcn.ballot.i64(i1 %or)
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%r = and i64 %r0, %r1
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ret i64 %r
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}
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