TheRock/compiler/amd-llvm/llvm/test/CodeGen/AMDGPU/rcp_iflag.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn < %s | FileCheck --check-prefix=GCN %s

define amdgpu_kernel void @rcp_uint(ptr addrspace(1) %in, ptr addrspace(1) %out) #0 {
; GCN-LABEL: rcp_uint:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    s_load_dword s0, s[0:1], 0x0
; GCN-NEXT:    s_mov_b32 s7, 0xf000
; GCN-NEXT:    s_mov_b32 s6, -1
; GCN-NEXT:    s_mov_b32 s4, s2
; GCN-NEXT:    s_mov_b32 s5, s3
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
; GCN-NEXT:    v_rcp_f32_e32 v0, v0
; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT:    s_endpgm
  %load = load i32, ptr addrspace(1) %in, align 4
  %cvt = uitofp i32 %load to float
  %div = fdiv float 1.000000e+00, %cvt, !fpmath !0
  store float %div, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @rcp_sint(ptr addrspace(1) %in, ptr addrspace(1) %out) #0 {
; GCN-LABEL: rcp_sint:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    s_load_dword s0, s[0:1], 0x0
; GCN-NEXT:    s_mov_b32 s7, 0xf000
; GCN-NEXT:    s_mov_b32 s6, -1
; GCN-NEXT:    s_mov_b32 s4, s2
; GCN-NEXT:    s_mov_b32 s5, s3
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
; GCN-NEXT:    v_rcp_f32_e32 v0, v0
; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT:    s_endpgm
  %load = load i32, ptr addrspace(1) %in, align 4
  %cvt = sitofp i32 %load to float
  %div = fdiv float 1.000000e+00, %cvt, !fpmath !0
  store float %div, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @rcp_uint_denorm(ptr addrspace(1) %in, ptr addrspace(1) %out) #1 {
; GCN-LABEL: rcp_uint_denorm:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    s_load_dword s0, s[0:1], 0x0
; GCN-NEXT:    s_mov_b32 s7, 0xf000
; GCN-NEXT:    s_mov_b32 s6, -1
; GCN-NEXT:    s_mov_b32 s4, s2
; GCN-NEXT:    s_mov_b32 s5, s3
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
; GCN-NEXT:    v_div_scale_f32 v1, s[0:1], v0, v0, 1.0
; GCN-NEXT:    v_rcp_f32_e32 v2, v1
; GCN-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
; GCN-NEXT:    v_fma_f32 v2, v3, v2, v2
; GCN-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
; GCN-NEXT:    v_mul_f32_e32 v4, v3, v2
; GCN-NEXT:    v_fma_f32 v5, -v1, v4, v3
; GCN-NEXT:    v_fma_f32 v4, v5, v2, v4
; GCN-NEXT:    v_fma_f32 v1, -v1, v4, v3
; GCN-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
; GCN-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT:    s_endpgm
  %load = load i32, ptr addrspace(1) %in, align 4
  %cvt = uitofp i32 %load to float
  %div = fdiv float 1.000000e+00, %cvt
  store float %div, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @rcp_sint_denorm(ptr addrspace(1) %in, ptr addrspace(1) %out) #1 {
; GCN-LABEL: rcp_sint_denorm:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    s_load_dword s0, s[0:1], 0x0
; GCN-NEXT:    s_mov_b32 s7, 0xf000
; GCN-NEXT:    s_mov_b32 s6, -1
; GCN-NEXT:    s_mov_b32 s4, s2
; GCN-NEXT:    s_mov_b32 s5, s3
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
; GCN-NEXT:    v_div_scale_f32 v1, s[0:1], v0, v0, 1.0
; GCN-NEXT:    v_rcp_f32_e32 v2, v1
; GCN-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
; GCN-NEXT:    v_fma_f32 v2, v3, v2, v2
; GCN-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
; GCN-NEXT:    v_mul_f32_e32 v4, v3, v2
; GCN-NEXT:    v_fma_f32 v5, -v1, v4, v3
; GCN-NEXT:    v_fma_f32 v4, v5, v2, v4
; GCN-NEXT:    v_fma_f32 v1, -v1, v4, v3
; GCN-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
; GCN-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT:    s_endpgm
  %load = load i32, ptr addrspace(1) %in, align 4
  %cvt = sitofp i32 %load to float
  %div = fdiv float 1.000000e+00, %cvt
  store float %div, ptr addrspace(1) %out, align 4
  ret void
}

!0 = !{float 2.500000e+00}

attributes #0 = { denormal_fpenv(float: preservesign) }
attributes #1 = { denormal_fpenv(float: ieee|ieee) }