derek.holloway
7502bf64a4
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51 lines
2.6 KiB
LLVM
51 lines
2.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --stress-regalloc=10 < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --stress-regalloc=10 < %s | FileCheck -check-prefix=GCN %s
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; Rematerialization test for fp64 constants (w/ intentionally high register pressure).
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; Check to make sure we have at least six constant MOVs, not necessarily consecutive, inside the loop.
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; GCN-LABEL: {{^}}test_remat_sgpr:
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; GCN-NOT: v_writelane_b32
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; GCN: {{^}}[[LOOP:.LBB[0-9_]+]]:
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; GCN-COUNT-6: {{s_mov_b32|v_mov_b32_e32}} {{[sv]}}{{[0-9]+}}, 0x
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; GCN-NOT: v_writelane_b32
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; GCN: s_cbranch_{{[^ ]+}} [[LOOP]]
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; GCN: .sgpr_spill_count: 0
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define amdgpu_kernel void @test_remat_sgpr(ptr addrspace(1) %arg, ptr addrspace(1) %arg1) #0 {
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bb:
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%i = tail call i32 @llvm.amdgcn.workitem.id.x()
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br label %bb3
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bb2: ; preds = %bb3
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ret void
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bb3: ; preds = %bb3, %bb
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%i4 = phi i32 [ 0, %bb ], [ %i22, %bb3 ]
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%i5 = add nuw nsw i32 %i4, %i
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%i6 = zext i32 %i5 to i64
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%i7 = getelementptr inbounds double, ptr addrspace(1) %arg, i64 %i6
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%i8 = load double, ptr addrspace(1) %i7, align 8
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%i9 = fadd double %i8, 0x3EFC01997CC9E6B0
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%i10 = tail call double @llvm.fma.f64(double %i8, double %i9, double 0x3FBE25E43ABE935A)
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%i11 = tail call double @llvm.fma.f64(double %i10, double %i9, double 0x3FC110EF47E6C9C2)
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%i12 = tail call double @llvm.fma.f64(double %i11, double %i9, double 0x3FC3B13BCFA74449)
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%i13 = tail call double @llvm.fma.f64(double %i12, double %i9, double 0x3FC745D171BF3C30)
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%i14 = tail call double @llvm.fma.f64(double %i13, double %i9, double 0x3FCC71C71C7792CE)
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%i15 = tail call double @llvm.fma.f64(double %i14, double %i9, double 0x3FD24924924920DA)
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%i16 = tail call double @llvm.fma.f64(double %i15, double %i9, double 0x3FD999999999999C)
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%i17 = tail call double @llvm.fma.f64(double %i16, double %i9, double 0x3FD899999999899C)
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%i18 = tail call double @llvm.fma.f64(double %i17, double %i9, double 0x3FD799999999799C)
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%i19 = tail call double @llvm.fma.f64(double %i18, double %i9, double 0x3FD699999999699C)
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%i20 = tail call double @llvm.fma.f64(double %i19, double %i9, double 0x3FD599999999599C)
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%i21 = getelementptr inbounds double, ptr addrspace(1) %arg1, i64 %i6
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store double %i19, ptr addrspace(1) %i21, align 8
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%i22 = add nuw nsw i32 %i4, 1
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%i23 = icmp eq i32 %i22, 1024
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br i1 %i23, label %bb2, label %bb3
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}
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declare double @llvm.fma.f64(double, double, double)
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declare i32 @llvm.amdgcn.workitem.id.x()
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attributes #0 = { "amdgpu-flat-work-group-size"="1024,1024" }
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