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73 lines
5.3 KiB
YAML
73 lines
5.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -passes="rename-independent-subregs,amdgpu-rewrite-partial-reg-uses" %s -o - | FileCheck -check-prefix=CHECK %s
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--- |
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define void @test_vreg_96_w64() !dbg !5 {
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entry:
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call void @llvm.dbg.value(metadata i32 0, metadata !9, metadata !DIExpression()), !dbg !11
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unreachable, !dbg !11
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}
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declare void @llvm.dbg.value(metadata, metadata, metadata) #0
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attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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!llvm.dbg.cu = !{!0}
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!llvm.mir.debugify = !{!2, !3}
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!llvm.debugify = !{!3, !3}
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!llvm.module.flags = !{!4}
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!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug)
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!1 = !DIFile(filename: "t.mir", directory: "/")
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!2 = !{i32 6}
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!3 = !{i32 1}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = distinct !DISubprogram(name: "test_vreg_96_w64", linkageName: "test_vreg_96_w64", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8)
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!6 = !DISubroutineType(types: !7)
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!7 = !{}
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!8 = !{!9}
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!9 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !10)
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!10 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned)
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!11 = !DILocation(line: 1, column: 1, scope: !5)
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...
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---
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name: test_vreg_96_w64
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body: |
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bb.0:
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; CHECK-LABEL: name: test_vreg_96_w64
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; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec, debug-location !11
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; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_]].sub0, $noreg, !9, !DIExpression(), debug-location !11
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec, debug-location !DILocation(line: 2, column: 1, scope: !5)
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; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_]].sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5)
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; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]], debug-location !DILocation(line: 3, column: 1, scope: !5)
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; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
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; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_1]].sub0, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
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; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
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; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_1]].sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
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; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]], debug-location !DILocation(line: 6, column: 1, scope: !5)
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; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
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; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_2]], $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
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; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
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; CHECK-NEXT: DBG_VALUE [[V_MOV_B32_e32_2]], $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
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; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]], debug-location !DILocation(line: 6, column: 1, scope: !5)
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undef %0.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec, debug-location !11
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DBG_VALUE %0.sub0, $noreg, !9, !DIExpression(), debug-location !11
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%0.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec, debug-location !DILocation(line: 2, column: 1, scope: !5)
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DBG_VALUE %0.sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 2, column: 1, scope: !5)
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S_NOP 0, implicit %0.sub0_sub1, debug-location !DILocation(line: 3, column: 1, scope: !5)
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undef %1.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
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DBG_VALUE %1.sub1, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
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%1.sub2:vreg_96 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
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DBG_VALUE %1.sub2, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
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S_NOP 0, implicit %1.sub1_sub2, debug-location !DILocation(line: 6, column: 1, scope: !5)
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undef %2.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec, debug-location !DILocation(line: 4, column: 1, scope: !5)
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DBG_VALUE %2, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 4, column: 1, scope: !5)
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%2.sub2:vreg_96 = V_MOV_B32_e32 12, implicit $exec, debug-location !DILocation(line: 5, column: 1, scope: !5)
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DBG_VALUE %2, $noreg, !9, !DIExpression(), debug-location !DILocation(line: 5, column: 1, scope: !5)
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S_NOP 0, implicit %2.sub1_sub2, debug-location !DILocation(line: 6, column: 1, scope: !5)
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...
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