derek.holloway
7502bf64a4
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434 lines
17 KiB
LLVM
434 lines
17 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 < %s | FileCheck %s
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; This was a negative test to catch an extreme case when all options are exhausted
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; while trying to spill SGPRs to memory. After we enabled SGPR spills into virtual VGPRs
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; the edge case won't arise and the test would always compile.
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define amdgpu_kernel void @kernel0(ptr addrspace(1) %out, i32 %in) #1 {
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; CHECK-LABEL: kernel0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[2:3]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ; implicit-def: $vgpr22 : SGPR spill to VGPR lane
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[4:7]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v22, s2, 0
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; CHECK-NEXT: v_writelane_b32 v22, s3, 1
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; CHECK-NEXT: v_writelane_b32 v22, s4, 2
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; CHECK-NEXT: v_writelane_b32 v22, s5, 3
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; CHECK-NEXT: v_writelane_b32 v22, s6, 4
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; CHECK-NEXT: s_load_dword s0, s[8:9], 0x8
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; CHECK-NEXT: v_writelane_b32 v22, s7, 5
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[4:11]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v22, s4, 6
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; CHECK-NEXT: v_writelane_b32 v22, s5, 7
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; CHECK-NEXT: v_writelane_b32 v22, s6, 8
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; CHECK-NEXT: v_writelane_b32 v22, s7, 9
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; CHECK-NEXT: v_writelane_b32 v22, s8, 10
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; CHECK-NEXT: v_writelane_b32 v22, s9, 11
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; CHECK-NEXT: v_writelane_b32 v22, s10, 12
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; CHECK-NEXT: v_writelane_b32 v22, s11, 13
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[4:19]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v22, s4, 14
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; CHECK-NEXT: v_writelane_b32 v22, s5, 15
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; CHECK-NEXT: v_writelane_b32 v22, s6, 16
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; CHECK-NEXT: v_writelane_b32 v22, s7, 17
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; CHECK-NEXT: v_writelane_b32 v22, s8, 18
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; CHECK-NEXT: v_writelane_b32 v22, s9, 19
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; CHECK-NEXT: v_writelane_b32 v22, s10, 20
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; CHECK-NEXT: v_writelane_b32 v22, s11, 21
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; CHECK-NEXT: v_writelane_b32 v22, s12, 22
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; CHECK-NEXT: v_writelane_b32 v22, s13, 23
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; CHECK-NEXT: v_writelane_b32 v22, s14, 24
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; CHECK-NEXT: v_writelane_b32 v22, s15, 25
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; CHECK-NEXT: v_writelane_b32 v22, s16, 26
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; CHECK-NEXT: v_writelane_b32 v22, s17, 27
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; CHECK-NEXT: v_writelane_b32 v22, s18, 28
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; CHECK-NEXT: v_writelane_b32 v22, s19, 29
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[34:35]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[36:39]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[4:11]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v22, s4, 30
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; CHECK-NEXT: v_writelane_b32 v22, s5, 31
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; CHECK-NEXT: v_writelane_b32 v22, s6, 32
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; CHECK-NEXT: v_writelane_b32 v22, s7, 33
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; CHECK-NEXT: v_writelane_b32 v22, s8, 34
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; CHECK-NEXT: v_writelane_b32 v22, s9, 35
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; CHECK-NEXT: v_writelane_b32 v22, s10, 36
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; CHECK-NEXT: v_writelane_b32 v22, s11, 37
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_cmp_lg_u32 s0, 0
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[16:31]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def vcc
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[40:43]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[44:51]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[0:15]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v22, s0, 38
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; CHECK-NEXT: v_writelane_b32 v22, s1, 39
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; CHECK-NEXT: v_writelane_b32 v22, s2, 40
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; CHECK-NEXT: v_writelane_b32 v22, s3, 41
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; CHECK-NEXT: v_writelane_b32 v22, s4, 42
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; CHECK-NEXT: v_writelane_b32 v22, s5, 43
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; CHECK-NEXT: v_writelane_b32 v22, s6, 44
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; CHECK-NEXT: v_writelane_b32 v22, s7, 45
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; CHECK-NEXT: v_writelane_b32 v22, s8, 46
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; CHECK-NEXT: v_writelane_b32 v22, s9, 47
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; CHECK-NEXT: v_writelane_b32 v22, s10, 48
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; CHECK-NEXT: v_writelane_b32 v22, s11, 49
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; CHECK-NEXT: v_writelane_b32 v22, s12, 50
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; CHECK-NEXT: v_writelane_b32 v22, s13, 51
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; CHECK-NEXT: v_writelane_b32 v22, s14, 52
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; CHECK-NEXT: v_writelane_b32 v22, s15, 53
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[0:1]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v22, s0, 54
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; CHECK-NEXT: v_writelane_b32 v22, s1, 55
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[0:3]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v22, s0, 56
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; CHECK-NEXT: v_writelane_b32 v22, s1, 57
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; CHECK-NEXT: v_writelane_b32 v22, s2, 58
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; CHECK-NEXT: v_writelane_b32 v22, s3, 59
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[0:7]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ; implicit-def: $vgpr23 : SGPR spill to VGPR lane
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; CHECK-NEXT: v_writelane_b32 v22, s0, 60
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; CHECK-NEXT: v_writelane_b32 v23, s4, 0
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; CHECK-NEXT: v_writelane_b32 v22, s1, 61
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; CHECK-NEXT: v_writelane_b32 v23, s5, 1
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; CHECK-NEXT: v_writelane_b32 v22, s2, 62
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; CHECK-NEXT: v_writelane_b32 v23, s6, 2
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; CHECK-NEXT: v_writelane_b32 v22, s3, 63
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; CHECK-NEXT: v_writelane_b32 v23, s7, 3
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[0:15]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v23, s0, 4
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; CHECK-NEXT: v_writelane_b32 v23, s1, 5
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; CHECK-NEXT: v_writelane_b32 v23, s2, 6
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; CHECK-NEXT: v_writelane_b32 v23, s3, 7
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; CHECK-NEXT: v_writelane_b32 v23, s4, 8
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; CHECK-NEXT: v_writelane_b32 v23, s5, 9
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; CHECK-NEXT: v_writelane_b32 v23, s6, 10
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; CHECK-NEXT: v_writelane_b32 v23, s7, 11
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; CHECK-NEXT: v_writelane_b32 v23, s8, 12
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; CHECK-NEXT: v_writelane_b32 v23, s9, 13
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; CHECK-NEXT: v_writelane_b32 v23, s10, 14
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; CHECK-NEXT: v_writelane_b32 v23, s11, 15
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; CHECK-NEXT: v_writelane_b32 v23, s12, 16
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; CHECK-NEXT: v_writelane_b32 v23, s13, 17
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; CHECK-NEXT: v_writelane_b32 v23, s14, 18
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; CHECK-NEXT: v_writelane_b32 v23, s15, 19
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[0:1]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v23, s0, 20
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; CHECK-NEXT: v_writelane_b32 v23, s1, 21
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[0:3]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v23, s0, 22
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; CHECK-NEXT: v_writelane_b32 v23, s1, 23
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; CHECK-NEXT: v_writelane_b32 v23, s2, 24
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; CHECK-NEXT: v_writelane_b32 v23, s3, 25
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[0:7]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v23, s0, 26
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; CHECK-NEXT: v_writelane_b32 v23, s1, 27
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; CHECK-NEXT: v_writelane_b32 v23, s2, 28
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; CHECK-NEXT: v_writelane_b32 v23, s3, 29
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; CHECK-NEXT: v_writelane_b32 v23, s4, 30
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; CHECK-NEXT: v_writelane_b32 v23, s5, 31
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; CHECK-NEXT: v_writelane_b32 v23, s6, 32
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; CHECK-NEXT: v_writelane_b32 v23, s7, 33
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; def s[0:15]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_writelane_b32 v23, s0, 34
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; CHECK-NEXT: v_writelane_b32 v23, s1, 35
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; CHECK-NEXT: v_writelane_b32 v23, s2, 36
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; CHECK-NEXT: v_writelane_b32 v23, s3, 37
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; CHECK-NEXT: v_writelane_b32 v23, s4, 38
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; CHECK-NEXT: v_writelane_b32 v23, s5, 39
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; CHECK-NEXT: v_writelane_b32 v23, s6, 40
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; CHECK-NEXT: v_writelane_b32 v23, s7, 41
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; CHECK-NEXT: v_writelane_b32 v23, s8, 42
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; CHECK-NEXT: v_writelane_b32 v23, s9, 43
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; CHECK-NEXT: v_writelane_b32 v23, s10, 44
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; CHECK-NEXT: v_writelane_b32 v23, s11, 45
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; CHECK-NEXT: v_writelane_b32 v23, s12, 46
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; CHECK-NEXT: v_writelane_b32 v23, s13, 47
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; CHECK-NEXT: v_writelane_b32 v23, s14, 48
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; CHECK-NEXT: v_writelane_b32 v23, s15, 49
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; CHECK-NEXT: s_cbranch_scc0 .LBB0_2
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; CHECK-NEXT: ; %bb.1: ; %ret
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: .LBB0_2: ; %bb0
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; CHECK-NEXT: v_readlane_b32 s0, v22, 0
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; CHECK-NEXT: v_readlane_b32 s1, v22, 1
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[0:1]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_readlane_b32 s0, v22, 2
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; CHECK-NEXT: v_readlane_b32 s1, v22, 3
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; CHECK-NEXT: v_readlane_b32 s2, v22, 4
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; CHECK-NEXT: v_readlane_b32 s3, v22, 5
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[0:3]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_readlane_b32 s0, v22, 6
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; CHECK-NEXT: v_readlane_b32 s1, v22, 7
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; CHECK-NEXT: v_readlane_b32 s2, v22, 8
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; CHECK-NEXT: v_readlane_b32 s3, v22, 9
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; CHECK-NEXT: v_readlane_b32 s4, v22, 10
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; CHECK-NEXT: v_readlane_b32 s5, v22, 11
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; CHECK-NEXT: v_readlane_b32 s6, v22, 12
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; CHECK-NEXT: v_readlane_b32 s7, v22, 13
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[0:7]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_readlane_b32 s0, v22, 14
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; CHECK-NEXT: v_readlane_b32 s1, v22, 15
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; CHECK-NEXT: v_readlane_b32 s2, v22, 16
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; CHECK-NEXT: v_readlane_b32 s3, v22, 17
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; CHECK-NEXT: v_readlane_b32 s4, v22, 18
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; CHECK-NEXT: v_readlane_b32 s5, v22, 19
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; CHECK-NEXT: v_readlane_b32 s6, v22, 20
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; CHECK-NEXT: v_readlane_b32 s7, v22, 21
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; CHECK-NEXT: v_readlane_b32 s8, v22, 22
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; CHECK-NEXT: v_readlane_b32 s9, v22, 23
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; CHECK-NEXT: v_readlane_b32 s10, v22, 24
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; CHECK-NEXT: v_readlane_b32 s11, v22, 25
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; CHECK-NEXT: v_readlane_b32 s12, v22, 26
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; CHECK-NEXT: v_readlane_b32 s13, v22, 27
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; CHECK-NEXT: v_readlane_b32 s14, v22, 28
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; CHECK-NEXT: v_readlane_b32 s15, v22, 29
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[0:15]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_readlane_b32 s0, v22, 30
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; CHECK-NEXT: v_readlane_b32 s1, v22, 31
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; CHECK-NEXT: v_readlane_b32 s2, v22, 32
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; CHECK-NEXT: v_readlane_b32 s3, v22, 33
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; CHECK-NEXT: v_readlane_b32 s4, v22, 34
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; CHECK-NEXT: v_readlane_b32 s5, v22, 35
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; CHECK-NEXT: v_readlane_b32 s6, v22, 36
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; CHECK-NEXT: v_readlane_b32 s7, v22, 37
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[34:35]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[36:39]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[0:7]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_readlane_b32 s0, v22, 38
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; CHECK-NEXT: v_readlane_b32 s1, v22, 39
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[16:31]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use vcc
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[40:43]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[44:51]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_readlane_b32 s2, v22, 40
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; CHECK-NEXT: v_readlane_b32 s3, v22, 41
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; CHECK-NEXT: v_readlane_b32 s4, v22, 42
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; CHECK-NEXT: v_readlane_b32 s5, v22, 43
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; CHECK-NEXT: v_readlane_b32 s6, v22, 44
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; CHECK-NEXT: v_readlane_b32 s7, v22, 45
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; CHECK-NEXT: v_readlane_b32 s8, v22, 46
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; CHECK-NEXT: v_readlane_b32 s9, v22, 47
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; CHECK-NEXT: v_readlane_b32 s10, v22, 48
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; CHECK-NEXT: v_readlane_b32 s11, v22, 49
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; CHECK-NEXT: v_readlane_b32 s12, v22, 50
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; CHECK-NEXT: v_readlane_b32 s13, v22, 51
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; CHECK-NEXT: v_readlane_b32 s14, v22, 52
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; CHECK-NEXT: v_readlane_b32 s15, v22, 53
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[0:15]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_readlane_b32 s0, v22, 54
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; CHECK-NEXT: v_readlane_b32 s1, v22, 55
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[0:1]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_readlane_b32 s0, v22, 56
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; CHECK-NEXT: v_readlane_b32 s1, v22, 57
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; CHECK-NEXT: v_readlane_b32 s2, v22, 58
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; CHECK-NEXT: v_readlane_b32 s3, v22, 59
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; use s[0:3]
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_readlane_b32 s0, v22, 60
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; CHECK-NEXT: v_readlane_b32 s1, v22, 61
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|
; CHECK-NEXT: v_readlane_b32 s2, v22, 62
|
|
; CHECK-NEXT: v_readlane_b32 s3, v22, 63
|
|
; CHECK-NEXT: v_readlane_b32 s4, v23, 0
|
|
; CHECK-NEXT: v_readlane_b32 s5, v23, 1
|
|
; CHECK-NEXT: v_readlane_b32 s6, v23, 2
|
|
; CHECK-NEXT: v_readlane_b32 s7, v23, 3
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use s[0:7]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_readlane_b32 s0, v23, 4
|
|
; CHECK-NEXT: v_readlane_b32 s1, v23, 5
|
|
; CHECK-NEXT: v_readlane_b32 s2, v23, 6
|
|
; CHECK-NEXT: v_readlane_b32 s3, v23, 7
|
|
; CHECK-NEXT: v_readlane_b32 s4, v23, 8
|
|
; CHECK-NEXT: v_readlane_b32 s5, v23, 9
|
|
; CHECK-NEXT: v_readlane_b32 s6, v23, 10
|
|
; CHECK-NEXT: v_readlane_b32 s7, v23, 11
|
|
; CHECK-NEXT: v_readlane_b32 s8, v23, 12
|
|
; CHECK-NEXT: v_readlane_b32 s9, v23, 13
|
|
; CHECK-NEXT: v_readlane_b32 s10, v23, 14
|
|
; CHECK-NEXT: v_readlane_b32 s11, v23, 15
|
|
; CHECK-NEXT: v_readlane_b32 s12, v23, 16
|
|
; CHECK-NEXT: v_readlane_b32 s13, v23, 17
|
|
; CHECK-NEXT: v_readlane_b32 s14, v23, 18
|
|
; CHECK-NEXT: v_readlane_b32 s15, v23, 19
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use s[0:15]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_readlane_b32 s0, v23, 20
|
|
; CHECK-NEXT: v_readlane_b32 s1, v23, 21
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use s[0:1]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_readlane_b32 s0, v23, 22
|
|
; CHECK-NEXT: v_readlane_b32 s1, v23, 23
|
|
; CHECK-NEXT: v_readlane_b32 s2, v23, 24
|
|
; CHECK-NEXT: v_readlane_b32 s3, v23, 25
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use s[0:3]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_readlane_b32 s0, v23, 26
|
|
; CHECK-NEXT: v_readlane_b32 s1, v23, 27
|
|
; CHECK-NEXT: v_readlane_b32 s2, v23, 28
|
|
; CHECK-NEXT: v_readlane_b32 s3, v23, 29
|
|
; CHECK-NEXT: v_readlane_b32 s4, v23, 30
|
|
; CHECK-NEXT: v_readlane_b32 s5, v23, 31
|
|
; CHECK-NEXT: v_readlane_b32 s6, v23, 32
|
|
; CHECK-NEXT: v_readlane_b32 s7, v23, 33
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use s[0:7]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_readlane_b32 s0, v23, 34
|
|
; CHECK-NEXT: v_readlane_b32 s1, v23, 35
|
|
; CHECK-NEXT: v_readlane_b32 s2, v23, 36
|
|
; CHECK-NEXT: v_readlane_b32 s3, v23, 37
|
|
; CHECK-NEXT: v_readlane_b32 s4, v23, 38
|
|
; CHECK-NEXT: v_readlane_b32 s5, v23, 39
|
|
; CHECK-NEXT: v_readlane_b32 s6, v23, 40
|
|
; CHECK-NEXT: v_readlane_b32 s7, v23, 41
|
|
; CHECK-NEXT: v_readlane_b32 s8, v23, 42
|
|
; CHECK-NEXT: v_readlane_b32 s9, v23, 43
|
|
; CHECK-NEXT: v_readlane_b32 s10, v23, 44
|
|
; CHECK-NEXT: v_readlane_b32 s11, v23, 45
|
|
; CHECK-NEXT: v_readlane_b32 s12, v23, 46
|
|
; CHECK-NEXT: v_readlane_b32 s13, v23, 47
|
|
; CHECK-NEXT: v_readlane_b32 s14, v23, 48
|
|
; CHECK-NEXT: v_readlane_b32 s15, v23, 49
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use s[0:15]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_endpgm
|
|
call void asm sideeffect "", "~{v[0:7]}" () #0
|
|
call void asm sideeffect "", "~{v[8:15]}" () #0
|
|
call void asm sideeffect "", "~{v[16:19]}"() #0
|
|
call void asm sideeffect "", "~{v[20:21]}"() #0
|
|
|
|
%val0 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val1 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val2 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val3 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val4 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val5 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val6 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val7 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val8 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val9 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val10 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val11 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val12 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val13 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val14 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val15 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val16 = call <2 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val17 = call <4 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val18 = call <8 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%val19 = call <16 x i32> asm sideeffect "; def $0", "=s" () #0
|
|
%cmp = icmp eq i32 %in, 0
|
|
br i1 %cmp, label %bb0, label %ret
|
|
|
|
bb0:
|
|
call void asm sideeffect "; use $0", "s"(<2 x i32> %val0) #0
|
|
call void asm sideeffect "; use $0", "s"(<4 x i32> %val1) #0
|
|
call void asm sideeffect "; use $0", "s"(<8 x i32> %val2) #0
|
|
call void asm sideeffect "; use $0", "s"(<16 x i32> %val3) #0
|
|
call void asm sideeffect "; use $0", "s"(<2 x i32> %val4) #0
|
|
call void asm sideeffect "; use $0", "s"(<4 x i32> %val5) #0
|
|
call void asm sideeffect "; use $0", "s"(<8 x i32> %val6) #0
|
|
call void asm sideeffect "; use $0", "s"(<16 x i32> %val7) #0
|
|
call void asm sideeffect "; use $0", "s"(<2 x i32> %val8) #0
|
|
call void asm sideeffect "; use $0", "s"(<4 x i32> %val9) #0
|
|
call void asm sideeffect "; use $0", "s"(<8 x i32> %val10) #0
|
|
call void asm sideeffect "; use $0", "s"(<16 x i32> %val11) #0
|
|
call void asm sideeffect "; use $0", "s"(<2 x i32> %val12) #0
|
|
call void asm sideeffect "; use $0", "s"(<4 x i32> %val13) #0
|
|
call void asm sideeffect "; use $0", "s"(<8 x i32> %val14) #0
|
|
call void asm sideeffect "; use $0", "s"(<16 x i32> %val15) #0
|
|
call void asm sideeffect "; use $0", "s"(<2 x i32> %val16) #0
|
|
call void asm sideeffect "; use $0", "s"(<4 x i32> %val17) #0
|
|
call void asm sideeffect "; use $0", "s"(<8 x i32> %val18) #0
|
|
call void asm sideeffect "; use $0", "s"(<16 x i32> %val19) #0
|
|
br label %ret
|
|
|
|
ret:
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind "amdgpu-waves-per-eu"="10,10" }
|