derek.holloway
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343 lines
20 KiB
YAML
343 lines
20 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -misched-cluster=false -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
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#
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# This test validates SCHED_GROUP_BARRIER pipelines that enforce a repeating
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# 2 LDSDMA loads + 1 compute scheduling pattern.
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--- |
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define amdgpu_kernel void @sched_group_barrier_mask_2048_tensor() { ret void }
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define amdgpu_kernel void @sched_group_barrier_mask_16_tensor() { ret void }
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define amdgpu_kernel void @sched_group_barrier_mask_2048_async_loads() { ret void }
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define amdgpu_kernel void @sched_group_barrier_mask_16_async_loads() { ret void }
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define amdgpu_kernel void @sched_group_barrier_mask_2048_interleave_2load_1valu() { ret void }
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...
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---
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name: sched_group_barrier_mask_2048_tensor
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: sched_group_barrier_mask_2048_tensor
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; CHECK: $exec = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF2:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF3:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF4:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF5:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF2]], [[DEF3]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF6]], [[DEF7]], implicit $exec
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF4]], [[DEF5]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF]], [[DEF3]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF8]], [[DEF9]], implicit $exec
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF2]], [[DEF5]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF4]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_ADD_U32_e32_]], [[V_ADD_U32_e32_1]], implicit $exec
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2048, 2, 0
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 0
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2048, 2, 0
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 0
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2048, 2, 0
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 0
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e32_]], implicit [[V_ADD_U32_e32_1]], implicit [[V_ADD_U32_e32_2]]
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$exec = IMPLICIT_DEF
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%0:sgpr_128 = IMPLICIT_DEF
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%1:sgpr_256 = IMPLICIT_DEF
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%2:sgpr_128 = IMPLICIT_DEF
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%3:sgpr_256 = IMPLICIT_DEF
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%4:sgpr_128 = IMPLICIT_DEF
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%5:sgpr_256 = IMPLICIT_DEF
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%20:vgpr_32 = IMPLICIT_DEF
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%21:vgpr_32 = IMPLICIT_DEF
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%22:vgpr_32 = IMPLICIT_DEF
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%23:vgpr_32 = IMPLICIT_DEF
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %0, %1, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %2, %3, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %4, %5, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %0, %3, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %2, %5, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %4, %1, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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%30:vgpr_32 = V_ADD_U32_e32 %20, %21, implicit $exec
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%31:vgpr_32 = V_ADD_U32_e32 %22, %23, implicit $exec
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%32:vgpr_32 = V_ADD_U32_e32 %30, %31, implicit $exec
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SCHED_GROUP_BARRIER 2048, 2, 0
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SCHED_GROUP_BARRIER 2, 1, 0
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SCHED_GROUP_BARRIER 2048, 2, 0
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SCHED_GROUP_BARRIER 2, 1, 0
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SCHED_GROUP_BARRIER 2048, 2, 0
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SCHED_GROUP_BARRIER 2, 1, 0
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S_ENDPGM 0, implicit %30, implicit %31, implicit %32
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...
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---
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name: sched_group_barrier_mask_16_tensor
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: sched_group_barrier_mask_16_tensor
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; CHECK: $exec = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF2:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF3:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF4:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF5:%[0-9]+]]:sgpr_256 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF2]], [[DEF3]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF6]], [[DEF7]], implicit $exec
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF4]], [[DEF5]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF]], [[DEF5]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_ADD_U32_e32_]], [[DEF8]], implicit $exec
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF2]], [[DEF1]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: TENSOR_LOAD_TO_LDS_d2_gfx1250 [[DEF4]], [[DEF3]], 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[V_ADD_U32_e32_1]], [[DEF9]], implicit $exec
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; CHECK-NEXT: SCHED_GROUP_BARRIER 16, 2, 2
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 2
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; CHECK-NEXT: SCHED_GROUP_BARRIER 16, 2, 2
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 2
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; CHECK-NEXT: SCHED_GROUP_BARRIER 16, 2, 2
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 2
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e32_]], implicit [[V_ADD_U32_e32_1]], implicit [[V_ADD_U32_e32_2]]
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$exec = IMPLICIT_DEF
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%0:sgpr_128 = IMPLICIT_DEF
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%1:sgpr_256 = IMPLICIT_DEF
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%2:sgpr_128 = IMPLICIT_DEF
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%3:sgpr_256 = IMPLICIT_DEF
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%4:sgpr_128 = IMPLICIT_DEF
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%5:sgpr_256 = IMPLICIT_DEF
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%20:vgpr_32 = IMPLICIT_DEF
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%21:vgpr_32 = IMPLICIT_DEF
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%22:vgpr_32 = IMPLICIT_DEF
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%23:vgpr_32 = IMPLICIT_DEF
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %0, %1, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %2, %3, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %4, %5, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %0, %5, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %2, %1, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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TENSOR_LOAD_TO_LDS_d2_gfx1250 %4, %3, 0, 0, implicit-def dead $tensorcnt, implicit $exec, implicit $tensorcnt
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%30:vgpr_32 = V_ADD_U32_e32 %20, %21, implicit $exec
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%31:vgpr_32 = V_ADD_U32_e32 %30, %22, implicit $exec
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%32:vgpr_32 = V_ADD_U32_e32 %31, %23, implicit $exec
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SCHED_GROUP_BARRIER 16, 2, 2
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SCHED_GROUP_BARRIER 2, 1, 2
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SCHED_GROUP_BARRIER 16, 2, 2
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SCHED_GROUP_BARRIER 2, 1, 2
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SCHED_GROUP_BARRIER 16, 2, 2
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SCHED_GROUP_BARRIER 2, 1, 2
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S_ENDPGM 0, implicit %30, implicit %31, implicit %32
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...
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---
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name: sched_group_barrier_mask_2048_async_loads
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: sched_group_barrier_mask_2048_async_loads
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; CHECK: $exec = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF10:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF6]], [[DEF]], 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF7]], [[DEF1]], 16, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF6]], [[DEF7]], implicit $exec
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; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF8]], [[DEF2]], 32, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF9]], [[DEF3]], 48, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF8]], [[DEF9]], implicit $exec
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; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF10]], [[DEF4]], 64, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF11]], [[DEF5]], 80, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF10]], [[DEF11]], implicit $exec
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2048, 2, 1
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 1
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2048, 2, 1
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 1
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2048, 2, 1
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; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 1
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e32_]], implicit [[V_ADD_U32_e32_1]], implicit [[V_ADD_U32_e32_2]]
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$exec = IMPLICIT_DEF
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%0:vreg_64_align2 = IMPLICIT_DEF
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%1:vreg_64_align2 = IMPLICIT_DEF
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%2:vreg_64_align2 = IMPLICIT_DEF
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%3:vreg_64_align2 = IMPLICIT_DEF
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%4:vreg_64_align2 = IMPLICIT_DEF
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%5:vreg_64_align2 = IMPLICIT_DEF
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%10:vgpr_32 = IMPLICIT_DEF
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%11:vgpr_32 = IMPLICIT_DEF
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%12:vgpr_32 = IMPLICIT_DEF
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%13:vgpr_32 = IMPLICIT_DEF
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%14:vgpr_32 = IMPLICIT_DEF
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%15:vgpr_32 = IMPLICIT_DEF
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GLOBAL_LOAD_ASYNC_TO_LDS_B32 %10, %0, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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GLOBAL_LOAD_ASYNC_TO_LDS_B32 %11, %1, 16, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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GLOBAL_LOAD_ASYNC_TO_LDS_B32 %12, %2, 32, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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GLOBAL_LOAD_ASYNC_TO_LDS_B32 %13, %3, 48, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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GLOBAL_LOAD_ASYNC_TO_LDS_B32 %14, %4, 64, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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GLOBAL_LOAD_ASYNC_TO_LDS_B32 %15, %5, 80, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
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%30:vgpr_32 = V_ADD_U32_e32 %10, %11, implicit $exec
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%31:vgpr_32 = V_ADD_U32_e32 %12, %13, implicit $exec
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%32:vgpr_32 = V_ADD_U32_e32 %14, %15, implicit $exec
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SCHED_GROUP_BARRIER 2048, 2, 1
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SCHED_GROUP_BARRIER 2, 1, 1
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SCHED_GROUP_BARRIER 2048, 2, 1
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SCHED_GROUP_BARRIER 2, 1, 1
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SCHED_GROUP_BARRIER 2048, 2, 1
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SCHED_GROUP_BARRIER 2, 1, 1
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S_ENDPGM 0, implicit %30, implicit %31, implicit %32
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...
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---
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name: sched_group_barrier_mask_16_async_loads
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: sched_group_barrier_mask_16_async_loads
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; CHECK: $exec = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF10:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: $m0 = S_MOV_B32 1
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; CHECK-NEXT: CLUSTER_LOAD_ASYNC_TO_LDS_B32 [[DEF6]], [[DEF]], 0, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: CLUSTER_LOAD_ASYNC_TO_LDS_B32 [[DEF7]], [[DEF1]], 16, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF6]], [[DEF8]], implicit $exec
|
|
; CHECK-NEXT: CLUSTER_LOAD_ASYNC_TO_LDS_B32 [[DEF8]], [[DEF2]], 32, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: CLUSTER_LOAD_ASYNC_TO_LDS_B32 [[DEF9]], [[DEF3]], 48, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF7]], [[DEF10]], implicit $exec
|
|
; CHECK-NEXT: CLUSTER_LOAD_ASYNC_TO_LDS_B32 [[DEF10]], [[DEF4]], 64, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: CLUSTER_LOAD_ASYNC_TO_LDS_B32 [[DEF11]], [[DEF5]], 80, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF9]], [[DEF11]], implicit $exec
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 16, 2, 3
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 3
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 16, 2, 3
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 3
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 16, 2, 3
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 3
|
|
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e32_]], implicit [[V_ADD_U32_e32_1]], implicit [[V_ADD_U32_e32_2]]
|
|
$exec = IMPLICIT_DEF
|
|
$m0 = S_MOV_B32 1
|
|
%0:vreg_64_align2 = IMPLICIT_DEF
|
|
%1:vreg_64_align2 = IMPLICIT_DEF
|
|
%2:vreg_64_align2 = IMPLICIT_DEF
|
|
%3:vreg_64_align2 = IMPLICIT_DEF
|
|
%4:vreg_64_align2 = IMPLICIT_DEF
|
|
%5:vreg_64_align2 = IMPLICIT_DEF
|
|
%10:vgpr_32 = IMPLICIT_DEF
|
|
%11:vgpr_32 = IMPLICIT_DEF
|
|
%12:vgpr_32 = IMPLICIT_DEF
|
|
%13:vgpr_32 = IMPLICIT_DEF
|
|
%14:vgpr_32 = IMPLICIT_DEF
|
|
%15:vgpr_32 = IMPLICIT_DEF
|
|
CLUSTER_LOAD_ASYNC_TO_LDS_B32 %10, %0, 0, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
CLUSTER_LOAD_ASYNC_TO_LDS_B32 %11, %1, 16, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
CLUSTER_LOAD_ASYNC_TO_LDS_B32 %12, %2, 32, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
CLUSTER_LOAD_ASYNC_TO_LDS_B32 %13, %3, 48, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
CLUSTER_LOAD_ASYNC_TO_LDS_B32 %14, %4, 64, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
CLUSTER_LOAD_ASYNC_TO_LDS_B32 %15, %5, 80, 0, implicit-def dead $asynccnt, implicit $m0, implicit $exec, implicit $asynccnt
|
|
%30:vgpr_32 = V_ADD_U32_e32 %10, %12, implicit $exec
|
|
%31:vgpr_32 = V_ADD_U32_e32 %11, %14, implicit $exec
|
|
%32:vgpr_32 = V_ADD_U32_e32 %13, %15, implicit $exec
|
|
SCHED_GROUP_BARRIER 16, 2, 3
|
|
SCHED_GROUP_BARRIER 2, 1, 3
|
|
SCHED_GROUP_BARRIER 16, 2, 3
|
|
SCHED_GROUP_BARRIER 2, 1, 3
|
|
SCHED_GROUP_BARRIER 16, 2, 3
|
|
SCHED_GROUP_BARRIER 2, 1, 3
|
|
S_ENDPGM 0, implicit %30, implicit %31, implicit %32
|
|
|
|
...
|
|
|
|
---
|
|
name: sched_group_barrier_mask_2048_interleave_2load_1valu
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
; CHECK-LABEL: name: sched_group_barrier_mask_2048_interleave_2load_1valu
|
|
; CHECK: $exec = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF2:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF3:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF4:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF5:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF10:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; CHECK-NEXT: [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
|
; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF6]], [[DEF]], 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF7]], [[DEF1]], 16, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF6]], [[DEF7]], implicit $exec
|
|
; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF8]], [[DEF2]], 32, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF9]], [[DEF3]], 48, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: [[V_ADD_U32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF8]], [[DEF9]], implicit $exec
|
|
; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF10]], [[DEF4]], 64, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B32 [[DEF11]], [[DEF5]], 80, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
; CHECK-NEXT: [[V_ADD_U32_e32_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 [[DEF10]], [[DEF11]], implicit $exec
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 2048, 2, 4
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 4
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 2048, 2, 4
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 4
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 2048, 2, 4
|
|
; CHECK-NEXT: SCHED_GROUP_BARRIER 2, 1, 4
|
|
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e32_]], implicit [[V_ADD_U32_e32_1]], implicit [[V_ADD_U32_e32_2]]
|
|
$exec = IMPLICIT_DEF
|
|
%0:vreg_64_align2 = IMPLICIT_DEF
|
|
%1:vreg_64_align2 = IMPLICIT_DEF
|
|
%2:vreg_64_align2 = IMPLICIT_DEF
|
|
%3:vreg_64_align2 = IMPLICIT_DEF
|
|
%4:vreg_64_align2 = IMPLICIT_DEF
|
|
%5:vreg_64_align2 = IMPLICIT_DEF
|
|
%10:vgpr_32 = IMPLICIT_DEF
|
|
%11:vgpr_32 = IMPLICIT_DEF
|
|
%12:vgpr_32 = IMPLICIT_DEF
|
|
%13:vgpr_32 = IMPLICIT_DEF
|
|
%14:vgpr_32 = IMPLICIT_DEF
|
|
%15:vgpr_32 = IMPLICIT_DEF
|
|
GLOBAL_LOAD_ASYNC_TO_LDS_B32 %10, %0, 0, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
GLOBAL_LOAD_ASYNC_TO_LDS_B32 %11, %1, 16, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
GLOBAL_LOAD_ASYNC_TO_LDS_B32 %12, %2, 32, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
GLOBAL_LOAD_ASYNC_TO_LDS_B32 %13, %3, 48, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
GLOBAL_LOAD_ASYNC_TO_LDS_B32 %14, %4, 64, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
GLOBAL_LOAD_ASYNC_TO_LDS_B32 %15, %5, 80, 0, implicit-def dead $asynccnt, implicit $exec, implicit $asynccnt
|
|
%30:vgpr_32 = V_ADD_U32_e32 %10, %11, implicit $exec
|
|
%31:vgpr_32 = V_ADD_U32_e32 %12, %13, implicit $exec
|
|
%32:vgpr_32 = V_ADD_U32_e32 %14, %15, implicit $exec
|
|
SCHED_GROUP_BARRIER 2048, 2, 4
|
|
SCHED_GROUP_BARRIER 2, 1, 4
|
|
SCHED_GROUP_BARRIER 2048, 2, 4
|
|
SCHED_GROUP_BARRIER 2, 1, 4
|
|
SCHED_GROUP_BARRIER 2048, 2, 4
|
|
SCHED_GROUP_BARRIER 2, 1, 4
|
|
S_ENDPGM 0, implicit %30, implicit %31, implicit %32
|
|
|
|
...
|