derek.holloway
7502bf64a4
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73 lines
2.6 KiB
LLVM
73 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck %s -check-prefix=GCN
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define amdgpu_cs void @should_not_hoist_set_inactive(<4 x i32> inreg %i14, i32 inreg %v, i32 %lane, i32 %f, i32 %f2) #0 {
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; GCN-LABEL: should_not_hoist_set_inactive:
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; GCN: ; %bb.0: ; %.entry
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; GCN-NEXT: v_cmp_eq_u32_e64 s5, 0, v0
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; GCN-NEXT: v_cmp_ne_u32_e64 s6, 0, v2
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; GCN-NEXT: s_mov_b32 s7, 0
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; GCN-NEXT: v_cmp_gt_i32_e32 vcc_lo, 3, v1
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; GCN-NEXT: s_branch .LBB0_2
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; GCN-NEXT: .LBB0_1: ; %bb4
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s8
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; GCN-NEXT: s_and_b32 s8, exec_lo, s6
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; GCN-NEXT: s_or_b32 s7, s8, s7
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; GCN-NEXT: s_andn2_b32 exec_lo, exec_lo, s7
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; GCN-NEXT: s_cbranch_execz .LBB0_5
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; GCN-NEXT: .LBB0_2: ; %bb
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_and_saveexec_b32 s8, vcc_lo
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; GCN-NEXT: s_cbranch_execz .LBB0_1
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; GCN-NEXT: ; %bb.3: ; %bb1
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: s_or_saveexec_b32 s9, -1
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; GCN-NEXT: v_cndmask_b32_e64 v3, 0, s4, s9
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; GCN-NEXT: v_mov_b32_e32 v4, 0
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; GCN-NEXT: v_mov_b32_dpp v4, v3 row_xmask:1 row_mask:0xf bank_mask:0xf
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; GCN-NEXT: s_mov_b32 exec_lo, s9
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; GCN-NEXT: v_mov_b32_e32 v0, v4
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; GCN-NEXT: s_and_b32 exec_lo, exec_lo, s5
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; GCN-NEXT: s_cbranch_execz .LBB0_1
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; GCN-NEXT: ; %bb.4: ; %bb2
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; GCN-NEXT: ; in Loop: Header=BB0_2 Depth=1
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; GCN-NEXT: buffer_atomic_add v0, off, s[0:3], 0
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; GCN-NEXT: s_branch .LBB0_1
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; GCN-NEXT: .LBB0_5: ; %bb5
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; GCN-NEXT: s_endpgm
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.entry:
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br label %bb
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bb:
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%i17 = icmp slt i32 %f, 3
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br i1 %i17, label %bb1, label %bb4
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bb1:
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%i25 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %v, i32 0)
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%i26 = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %i25, i32 353, i32 15, i32 15, i1 false)
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%i38 = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %i26)
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%i39 = icmp eq i32 %lane, 0
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br i1 %i39, label %bb2, label %bb3
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bb2:
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%i41 = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %i38, <4 x i32> %i14, i32 0, i32 0, i32 0)
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br label %bb3
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bb3:
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br label %bb4
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bb4:
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%exit = icmp eq i32 %f2, 0
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br i1 %exit, label %bb, label %bb5
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bb5:
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ret void
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}
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declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32)
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declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32 immarg, i32 immarg, i32 immarg, i1 immarg)
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declare i32 @llvm.amdgcn.strict.wwm.i32(i32)
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declare i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i32 immarg)
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