derek.holloway
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62 lines
2.8 KiB
LLVM
62 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s
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; This test is designed to check that the backedge from a prior block won't
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; reset the variable introduced to record and accumulate the number of threads
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; which have already exited the loop.
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define amdgpu_kernel void @multiple_backedges(i32 %arg, ptr %arg1) {
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; OPT-LABEL: @multiple_backedges(
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; OPT-NEXT: entry:
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; OPT-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
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; OPT-NEXT: [[TMP2:%.*]] = shl nsw i32 [[ARG:%.*]], 1
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; OPT-NEXT: br label [[LOOP:%.*]]
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; OPT: loop:
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; OPT-NEXT: [[PHI_BROKEN1:%.*]] = phi i64 [ [[TMP7:%.*]], [[LOOP_END:%.*]] ], [ [[PHI_BROKEN1]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
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; OPT-NEXT: [[PHI_BROKEN:%.*]] = phi i64 [ 0, [[LOOP_END]] ], [ [[TMP0:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
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; OPT-NEXT: [[TMP4:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP5:%.*]], [[LOOP]] ], [ 0, [[LOOP_END]] ]
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; OPT-NEXT: [[TMP5]] = add nsw i32 [[TMP4]], [[TMP]]
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; OPT-NEXT: [[TMP6:%.*]] = icmp slt i32 [[ARG]], [[TMP5]]
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; OPT-NEXT: [[TMP0]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[TMP6]], i64 [[PHI_BROKEN]])
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; OPT-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP0]])
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; OPT-NEXT: br i1 [[TMP1]], label [[LOOP_END]], label [[LOOP]]
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; OPT: loop_end:
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP0]])
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; OPT-NEXT: [[EXIT:%.*]] = icmp sgt i32 [[TMP5]], [[TMP2]]
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; OPT-NEXT: [[TMP7]] = call i64 @llvm.amdgcn.if.break.i64(i1 [[EXIT]], i64 [[PHI_BROKEN1]])
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; OPT-NEXT: [[TMP3:%.*]] = call i1 @llvm.amdgcn.loop.i64(i64 [[TMP7]])
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; OPT-NEXT: br i1 [[TMP3]], label [[LOOP_EXIT:%.*]], label [[LOOP]]
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; OPT: loop_exit:
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; OPT-NEXT: call void @llvm.amdgcn.end.cf.i64(i64 [[TMP7]])
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; OPT-NEXT: [[TMP12:%.*]] = zext i32 [[TMP]] to i64
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; OPT-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[ARG1:%.*]], i64 [[TMP12]]
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; OPT-NEXT: [[TMP14:%.*]] = addrspacecast ptr [[TMP13]] to ptr addrspace(1)
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; OPT-NEXT: store i32 [[TMP5]], ptr addrspace(1) [[TMP14]], align 4
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; OPT-NEXT: ret void
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;
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entry:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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%tmp2 = shl nsw i32 %arg, 1
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br label %loop
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loop:
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%tmp4 = phi i32 [ 0, %entry ], [ %tmp5, %loop ], [ 0, %loop_end ]
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%tmp5 = add nsw i32 %tmp4, %tmp
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%tmp6 = icmp slt i32 %arg, %tmp5
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br i1 %tmp6, label %loop_end, label %loop
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loop_end:
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%exit = icmp sgt i32 %tmp5, %tmp2
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br i1 %exit, label %loop_exit, label %loop
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loop_exit:
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%tmp12 = zext i32 %tmp to i64
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%tmp13 = getelementptr inbounds i32, ptr %arg1, i64 %tmp12
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%tmp14 = addrspacecast ptr %tmp13 to ptr addrspace(1)
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store i32 %tmp5, ptr addrspace(1) %tmp14, align 4
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ret void
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}
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; Function Attrs: nounwind readnone speculatable
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declare i32 @llvm.amdgcn.workitem.id.x()
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