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115 lines
5.7 KiB
YAML
115 lines
5.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR-SPILL %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -O0 -start-before=si-lower-sgpr-spills -stop-after=regallocfast,1 -verify-machineinstrs %s -o - | FileCheck -check-prefix=WWM-REGALLOC %s
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# When SGPR spills to a virtual VGPR lane occur in both a loop header and the latch,
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# the IMPLICIT_DEF for the lane VGPR must be placed in the preheader (not the header).
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# Establish that the virtual VGPR is live-in to the header and wwm regallocfast inserts
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# a restore, preserving the latch writes.
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---
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name: sgpr_spill_loop_header_and_latch_implicit_def_in_preheader
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 4
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stack:
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- { id: 0, type: spill-slot, size: 4, alignment: 4, stack-id: sgpr-spill }
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machineFunctionInfo:
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isEntryFunction: false
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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frameOffsetReg: '$sgpr33'
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hasSpilledSGPRs: true
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body: |
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; SGPR-SPILL-LABEL: name: sgpr_spill_loop_header_and_latch_implicit_def_in_preheader
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; SGPR-SPILL: bb.0:
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; SGPR-SPILL-NEXT: successors: %bb.1(0x80000000)
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; SGPR-SPILL-NEXT: liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
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; SGPR-SPILL-NEXT: {{ $}}
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; SGPR-SPILL-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; SGPR-SPILL-NEXT: S_BRANCH %bb.1
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; SGPR-SPILL-NEXT: {{ $}}
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; SGPR-SPILL-NEXT: bb.1:
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; SGPR-SPILL-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
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; SGPR-SPILL-NEXT: liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
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; SGPR-SPILL-NEXT: {{ $}}
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; SGPR-SPILL-NEXT: $sgpr10 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
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; SGPR-SPILL-NEXT: S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
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; SGPR-SPILL-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]
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; SGPR-SPILL-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc
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; SGPR-SPILL-NEXT: S_BRANCH %bb.3
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; SGPR-SPILL-NEXT: {{ $}}
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; SGPR-SPILL-NEXT: bb.2:
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; SGPR-SPILL-NEXT: successors: %bb.1(0x80000000)
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; SGPR-SPILL-NEXT: liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
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; SGPR-SPILL-NEXT: {{ $}}
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; SGPR-SPILL-NEXT: $sgpr10 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
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; SGPR-SPILL-NEXT: $sgpr10 = S_MOV_B32 1
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; SGPR-SPILL-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR killed $sgpr10, 0, [[DEF]]
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; SGPR-SPILL-NEXT: S_BRANCH %bb.1
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; SGPR-SPILL-NEXT: {{ $}}
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; SGPR-SPILL-NEXT: bb.3:
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; SGPR-SPILL-NEXT: liveins: $sgpr30_sgpr31
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; SGPR-SPILL-NEXT: {{ $}}
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; SGPR-SPILL-NEXT: S_SETPC_B64 $sgpr30_sgpr31
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;
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; WWM-REGALLOC-LABEL: name: sgpr_spill_loop_header_and_latch_implicit_def_in_preheader
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; WWM-REGALLOC: bb.0:
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; WWM-REGALLOC-NEXT: successors: %bb.1(0x80000000)
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; WWM-REGALLOC-NEXT: liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
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; WWM-REGALLOC-NEXT: {{ $}}
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; WWM-REGALLOC-NEXT: renamable $vgpr63 = IMPLICIT_DEF
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; WWM-REGALLOC-NEXT: S_BRANCH %bb.1
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; WWM-REGALLOC-NEXT: {{ $}}
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; WWM-REGALLOC-NEXT: bb.1:
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; WWM-REGALLOC-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
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; WWM-REGALLOC-NEXT: liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
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; WWM-REGALLOC-NEXT: {{ $}}
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; WWM-REGALLOC-NEXT: $vgpr63 = SI_SPILL_WWM_V32_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5)
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; WWM-REGALLOC-NEXT: $sgpr10 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 0
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; WWM-REGALLOC-NEXT: S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
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; WWM-REGALLOC-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr10, 0, $vgpr63
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; WWM-REGALLOC-NEXT: SI_SPILL_WWM_V32_SAVE killed $vgpr63, %stack.1, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
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; WWM-REGALLOC-NEXT: S_CBRANCH_SCC1 %bb.2, implicit killed $scc
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; WWM-REGALLOC-NEXT: S_BRANCH %bb.3
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; WWM-REGALLOC-NEXT: {{ $}}
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; WWM-REGALLOC-NEXT: bb.2:
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; WWM-REGALLOC-NEXT: successors: %bb.1(0x80000000)
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; WWM-REGALLOC-NEXT: liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
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; WWM-REGALLOC-NEXT: {{ $}}
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; WWM-REGALLOC-NEXT: $vgpr63 = SI_SPILL_WWM_V32_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.1, addrspace 5)
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; WWM-REGALLOC-NEXT: dead $sgpr10 = SI_RESTORE_S32_FROM_VGPR $vgpr63, 0
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; WWM-REGALLOC-NEXT: $sgpr10 = S_MOV_B32 1
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; WWM-REGALLOC-NEXT: $vgpr63 = SI_SPILL_S32_TO_VGPR $sgpr10, 0, $vgpr63
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; WWM-REGALLOC-NEXT: SI_SPILL_WWM_V32_SAVE killed $vgpr63, %stack.1, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
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; WWM-REGALLOC-NEXT: S_BRANCH %bb.1
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; WWM-REGALLOC-NEXT: {{ $}}
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; WWM-REGALLOC-NEXT: bb.3:
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; WWM-REGALLOC-NEXT: liveins: $sgpr30_sgpr31
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; WWM-REGALLOC-NEXT: {{ $}}
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; WWM-REGALLOC-NEXT: S_SETPC_B64 killed $sgpr30_sgpr31
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bb.0:
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liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
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S_BRANCH %bb.1
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bb.1:
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liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
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renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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S_CMP_EQ_U32 $sgpr11, 0, implicit-def $scc
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SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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S_CBRANCH_SCC1 %bb.2, implicit killed $scc
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S_BRANCH %bb.3
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bb.2:
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liveins: $sgpr10, $sgpr11, $sgpr30_sgpr31
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renamable $sgpr10 = SI_SPILL_S32_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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$sgpr10 = S_MOV_B32 1
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SI_SPILL_S32_SAVE killed $sgpr10, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32
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S_BRANCH %bb.1
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bb.3:
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liveins: $sgpr30_sgpr31
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S_SETPC_B64 $sgpr30_sgpr31
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## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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