derek.holloway
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53 lines
2.5 KiB
YAML
53 lines
2.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -passes si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
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# Skip folding a REG_SEQUENCE to its user when the regclasses for the user operands can't be
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# fully determined from the instruction description.
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---
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name: regsequence_with_regsequence_use_op
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $agpr0, $agpr1
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; GCN-LABEL: name: regsequence_with_regsequence_use_op
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; GCN: liveins: $agpr0, $agpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr0
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr1
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, killed [[DEF]], %subreg.sub2
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; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]
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%0:vgpr_32 = COPY $agpr0
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%1:vgpr_32 = COPY $agpr1
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%2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1
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%3:vgpr_32 = IMPLICIT_DEF
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%4:vreg_96_align2 = REG_SEQUENCE killed %2:vreg_64_align2, %subreg.sub0_sub1, killed %3:vgpr_32, %subreg.sub2
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S_ENDPGM 0, implicit %4
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...
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---
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name: insert_subreg_with_regsequence_use_op
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $agpr0, $agpr1
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; GCN-LABEL: name: insert_subreg_with_regsequence_use_op
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; GCN: liveins: $agpr0, $agpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr0
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr1
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
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; GCN-NEXT: S_NOP 0, implicit-def %3
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; GCN-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64_align2 = INSERT_SUBREG %3, [[REG_SEQUENCE]], %subreg.sub0_sub1
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; GCN-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
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%0:vgpr_32 = COPY $agpr0
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%1:vgpr_32 = COPY $agpr1
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%2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1
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S_NOP 0, implicit-def %3:vreg_64_align2
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%4:vreg_64_align2 = INSERT_SUBREG %3, %2, %subreg.sub0_sub1
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S_ENDPGM 0, implicit %4
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...
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