derek.holloway
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59 lines
2.3 KiB
LLVM
59 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -o - %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -o - %s | FileCheck -check-prefix=GCN %s
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; Callee must preserve the VGPR modified by writelane even if it is marked Caller-saved.
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declare i32 @llvm.amdgcn.writelane(i32, i32, i32)
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define void @sgpr_spill_writelane() {
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; GCN-LABEL: sgpr_spill_writelane:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec, s[4:5]
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; GCN-NEXT: v_writelane_b32 v0, s35, 0
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: v_readlane_b32 s35, v0, 0
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; GCN-NEXT: s_xor_saveexec_b64 s[4:5], -1
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; GCN-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
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; GCN-NEXT: s_mov_b64 exec, s[4:5]
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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call void asm sideeffect "", "~{s35}"()
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ret void
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}
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define void @device_writelane_intrinsic(ptr addrspace(1) %out, i32 %src) {
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; GCN-LABEL: device_writelane_intrinsic:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v3, 15
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; GCN-NEXT: v_readfirstlane_b32 s4, v2
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; GCN-NEXT: v_writelane_b32 v3, s4, 23
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; GCN-NEXT: global_store_dword v[0:1], v3, off
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%writelane = call i32 @llvm.amdgcn.writelane(i32 %src, i32 23, i32 15)
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store i32 %writelane, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @kernel_writelane_intrinsic(ptr addrspace(1) %out, i32 %src0, i32 %src1) {
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; GCN-LABEL: kernel_writelane_intrinsic:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0
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; GCN-NEXT: v_mov_b32_e32 v1, 45
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b32 m0, s3
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; GCN-NEXT: v_writelane_b32 v1, s2, m0
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; GCN-NEXT: global_store_dword v0, v1, s[0:1]
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; GCN-NEXT: s_endpgm
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%writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 45)
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store i32 %writelane, ptr addrspace(1) %out, align 4
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ret void
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}
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