derek.holloway
7502bf64a4
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169 lines
7.2 KiB
YAML
169 lines
7.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-regalloc -run-pass=greedy -o - %s | FileCheck %s
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# Check that liverange splitting does not create copies that overlap within a bundle.
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# By overlap, we mean that they write to the same subregisters.
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# e.g. the following bundle is desirable
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# %0.sub1_sub2 = COPY ... {
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# %0.sub3 = COPY ...
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# }
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# but the following bundle isn't desirable as the overlap of the copies can make
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# virtregrewriter fail due to cycles in the copy bundle.
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# %0.sub1_sub2 = COPY ... {
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# %0.sub2_sub3 = COPY ...
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# }
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---
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name: split_liverange_copy_overlap_31
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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occupancy: 7
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body: |
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; CHECK-LABEL: name: split_liverange_copy_overlap_31
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
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; CHECK-NEXT: [[COPY:%[0-9]+]]:av_1024_align2 = COPY [[DEF1]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK-NEXT: S_NOP 0, implicit [[DEF1]]
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; CHECK-NEXT: S_NOP 0, implicit [[DEF1]]
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024_align2 = IMPLICIT_DEF
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16:av_1024_align2 = COPY [[COPY]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16 {
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; CHECK-NEXT: internal [[COPY1]].sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16:av_1024_align2 = COPY [[COPY]].sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16_sub29_lo16_sub29_hi16_sub30_lo16_sub30_hi16_sub31_lo16_sub31_hi16
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; CHECK-NEXT: internal [[COPY1]].sub17_sub18_sub19:av_1024_align2 = COPY [[COPY]].sub17_sub18_sub19
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; CHECK-NEXT: }
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; CHECK-NEXT: [[COPY1:%[0-9]+]].sub0:av_1024_align2 = IMPLICIT_DEF
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; CHECK-NEXT: S_NOP 0, implicit [[COPY1]].sub0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:av_1024_align2 = IMPLICIT_DEF
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.5:
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; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:vreg_1024_align2 = COPY [[DEF]]
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; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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%1:vreg_1024_align2 = IMPLICIT_DEF
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%2:vreg_1024_align2 = COPY %1
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bb.1:
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%5:vreg_64 = IMPLICIT_DEF
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S_NOP 0, implicit %1
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S_NOP 0, implicit %1
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%1:vreg_1024_align2 = IMPLICIT_DEF
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S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
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bb.2:
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%2.sub0:vreg_1024_align2 = IMPLICIT_DEF
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S_NOP 0, implicit %2.sub0
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bb.3:
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S_NOP 0, implicit %2
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bb.4:
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%2:vreg_1024_align2 = IMPLICIT_DEF
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S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc
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bb.5:
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undef %4.sub0:vreg_1024_align2 = COPY %0
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S_NOP 0, implicit %4
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...
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---
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name: split_liverange_copy_overlap_30
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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stackPtrOffsetReg: '$sgpr32'
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occupancy: 7
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body: |
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; CHECK-LABEL: name: split_liverange_copy_overlap_30
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF
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; CHECK-NEXT: [[COPY:%[0-9]+]]:av_1024 = COPY [[DEF1]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK-NEXT: S_NOP 0, implicit [[DEF1]]
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; CHECK-NEXT: S_NOP 0, implicit [[DEF1]]
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[COPY1:%[0-9]+]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16:av_1024 = COPY [[COPY]].sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16 {
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; CHECK-NEXT: internal [[COPY1]].sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16:av_1024 = COPY [[COPY]].sub17_lo16_sub17_hi16_sub18_lo16_sub18_hi16_sub19_lo16_sub19_hi16_sub20_lo16_sub20_hi16_sub21_lo16_sub21_hi16_sub22_lo16_sub22_hi16_sub23_lo16_sub23_hi16_sub24_lo16_sub24_hi16_sub25_lo16_sub25_hi16_sub26_lo16_sub26_hi16_sub27_lo16_sub27_hi16_sub28_lo16_sub28_hi16
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; CHECK-NEXT: internal [[COPY1]].sub29_sub30:av_1024 = COPY [[COPY]].sub29_sub30
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; CHECK-NEXT: }
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; CHECK-NEXT: [[COPY1:%[0-9]+]].sub0:av_1024 = IMPLICIT_DEF
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; CHECK-NEXT: [[COPY1:%[0-9]+]].sub31:av_1024 = IMPLICIT_DEF
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; CHECK-NEXT: S_NOP 0, implicit [[COPY1]].sub0, implicit [[COPY1]].sub31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_NOP 0, implicit [[COPY1]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:av_1024 = IMPLICIT_DEF
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.5:
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; CHECK-NEXT: undef [[COPY2:%[0-9]+]].sub0:vreg_1024 = COPY [[DEF]]
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; CHECK-NEXT: S_NOP 0, implicit [[COPY2]]
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bb.0:
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%0:vgpr_32 = IMPLICIT_DEF
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%1:vreg_1024 = IMPLICIT_DEF
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%2:vreg_1024 = COPY %1
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bb.1:
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%5:vreg_64 = IMPLICIT_DEF
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S_NOP 0, implicit %1
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S_NOP 0, implicit %1
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%1:vreg_1024 = IMPLICIT_DEF
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S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
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bb.2:
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%2.sub0:vreg_1024 = IMPLICIT_DEF
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%2.sub31:vreg_1024 = IMPLICIT_DEF
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S_NOP 0, implicit %2.sub0, implicit %2.sub31
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bb.3:
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S_NOP 0, implicit %2
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bb.4:
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%2:vreg_1024 = IMPLICIT_DEF
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S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc
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bb.5:
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undef %4.sub0:vreg_1024 = COPY %0
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S_NOP 0, implicit %4
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...
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