derek.holloway
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93 lines
4.4 KiB
YAML
93 lines
4.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
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# Deciding which lanes are killed needs to account for other defs in the
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# instruction.
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#
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# addVRegDefDeps would encounter the %0.sub0 def and erase %0 from
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# current vreg uses because it shared no lanes with %0.sub1 use on the
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# nop. It then didn't see the lanemask when it reached the second
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# subreg def, and failed to add the necessary dependency between the
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# asm and S_NOP
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---
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name: no_live_subrange_at_use
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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; CHECK-LABEL: name: no_live_subrange_at_use
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (load (s32), addrspace 3)
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; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def [[V_MOV_B32_e32_]], reguse tiedto:$0, [[V_MOV_B32_e32_]](tied-def 3)
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; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, reguse:VGPR_32, [[DS_READ_B32_gfx9_]]
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; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub0, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub1
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; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1
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; CHECK-NEXT: $sgpr10 = S_MOV_B32 -1
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; CHECK-NEXT: S_BRANCH %bb.1
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bb.0:
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undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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%0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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bb.1:
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%2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load (s32), addrspace 3)
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INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def %0, reguse tiedto:$0, %0(tied-def 3)
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INLINEASM &"", sideeffect attdialect, reguse:VGPR_32, %2
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INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def undef %0.sub0, regdef:VGPR_32, def %0.sub1
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S_NOP 0, implicit %0.sub1
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$sgpr10 = S_MOV_B32 -1
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S_BRANCH %bb.1
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...
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# Different operand order
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---
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name: no_live_subrange_at_use_swap
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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body: |
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; CHECK-LABEL: name: no_live_subrange_at_use_swap
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (load (s32), addrspace 3)
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; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def [[V_MOV_B32_e32_]], reguse tiedto:$0, [[V_MOV_B32_e32_]](tied-def 3)
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; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, reguse:VGPR_32, [[DS_READ_B32_gfx9_]]
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; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub1, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub0
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; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1
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; CHECK-NEXT: $sgpr10 = S_MOV_B32 -1
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; CHECK-NEXT: S_BRANCH %bb.1
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bb.0:
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undef %0.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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%0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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%1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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bb.1:
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%2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load (s32), addrspace 3)
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INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def %0, reguse tiedto:$0, %0(tied-def 3)
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INLINEASM &"", sideeffect attdialect, reguse:VGPR_32, %2
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INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def %0.sub1, regdef:VGPR_32, def undef %0.sub0
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S_NOP 0, implicit %0.sub1
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$sgpr10 = S_MOV_B32 -1
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S_BRANCH %bb.1
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...
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