derek.holloway
7502bf64a4
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86 lines
3.7 KiB
LLVM
86 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stress-regalloc=4 -o - %s | FileCheck %s
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; Make sure we can rematerialize split 64-bit constants (which
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; MachineLICM hoisted out of the loop) and avoid spilling inside the
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; loop.
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;
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; MachineLICM originally believed the constant materializes to be
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; rematerializable, but the lowered REG_SEQUENCE uses they coalesece
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; into were not. The InlineSpiller also did not recognize redundant
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; spills inside the loop, so we would repeatedly reload the same
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; values.
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define amdgpu_kernel void @_Z6kernelILi4000ELi1EEvPd(ptr addrspace(1) %x.coerce) {
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; CHECK-LABEL: _Z6kernelILi4000ELi1EEvPd:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_mov_b64 s[2:3], 0x100
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; CHECK-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x0
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; CHECK-NEXT: s_mov_b64 s[0:1], 0
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; CHECK-NEXT: s_load_dword s0, s[0:1], 0x0
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; CHECK-NEXT: s_mov_b32 s1, 0
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; CHECK-NEXT: s_mov_b32 s2, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, s6
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; CHECK-NEXT: s_mov_b32 s3, 0x40260000
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: s_mov_b32 s5, 0x40280000
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; CHECK-NEXT: v_mov_b32_e32 v1, s7
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; CHECK-NEXT: .LBB0_1: ; %for.cond4.preheader
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s7, 0x40140000
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; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s7, 0x40180000
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; CHECK-NEXT: s_add_i32 s1, s1, s0
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; CHECK-NEXT: s_cmpk_lt_i32 s1, 0xa00
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; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s7, 0x401c0000
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; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s7, 0x40220000
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; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
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; CHECK-NEXT: s_mov_b32 s6, 0
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; CHECK-NEXT: s_mov_b32 s7, 0x40240000
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; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[6:7]
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; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[2:3]
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; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], s[4:5]
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; CHECK-NEXT: s_cbranch_scc1 .LBB0_1
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; CHECK-NEXT: ; %bb.2: ; %for.cond.cleanup.loopexit
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; CHECK-NEXT: v_mov_b32_e32 v2, 0x100
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; CHECK-NEXT: v_mov_b32_e32 v3, 0
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; CHECK-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
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; CHECK-NEXT: s_endpgm
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entry:
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%0 = load i32, ptr addrspace(4) null, align 4
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%cmp6 = icmp slt i32 0, 2560
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br i1 %cmp6, label %for.cond4.preheader, label %for.cond.cleanup
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for.cond4.preheader: ; preds = %for.cond4.preheader, %entry
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%idx.07 = phi i32 [ %add13, %for.cond4.preheader ], [ 0, %entry ]
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%arrayidx.promoted = load double, ptr addrspace(1) inttoptr (i64 256 to ptr addrspace(1)), align 8
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%add9 = fadd contract double %arrayidx.promoted, 0.000000e+00
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%add9.1 = fadd contract double %add9, 5.000000e+00
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%add9.2 = fadd contract double %add9.1, 6.000000e+00
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%add9.3 = fadd contract double %add9.2, 7.000000e+00
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%add9.4 = fadd contract double %add9.3, 9.000000e+00
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%add9.5 = fadd contract double %add9.4, 1.000000e+01
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%add9.6 = fadd contract double %add9.5, 1.100000e+01
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%add9.7 = fadd contract double %add9.6, 1.200000e+01
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store double %add9.7, ptr addrspace(1) inttoptr (i64 256 to ptr addrspace(1)), align 8
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%add13 = add i32 %idx.07, %0
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%cmp = icmp slt i32 %add13, 2560
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br i1 %cmp, label %for.cond4.preheader, label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond4.preheader, %entry
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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declare align 4 ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #0
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attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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