derek.holloway
7502bf64a4
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38 lines
1.4 KiB
LLVM
38 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
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; The tail call target is known uniform, but will be in a VGPR, so we
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; need readfirstlane to legalize it.
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define void @tail_call_uniform_vgpr_value() {
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; CHECK-LABEL: tail_call_uniform_vgpr_value:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: ds_read_b64 v[0:1], v0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s17, v1
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; CHECK-NEXT: v_readfirstlane_b32 s16, v0
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; CHECK-NEXT: s_setpc_b64 s[16:17]
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%fptr = load ptr, ptr addrspace(3) zeroinitializer, align 8
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tail call void %fptr()
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ret void
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}
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@constant = external hidden addrspace(4) constant ptr
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; readfirstlanes should fold out.
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define void @tail_call_uniform_sgpr_value() {
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; CHECK-LABEL: tail_call_uniform_sgpr_value:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_getpc_b64 s[16:17]
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; CHECK-NEXT: s_add_u32 s16, s16, constant@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s17, s17, constant@rel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[16:17]
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%fptr = load ptr, ptr addrspace(4) @constant, align 8
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tail call void %fptr()
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ret void
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}
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