derek.holloway
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72 lines
2.7 KiB
LLVM
72 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+wavefrontsize64 --global-isel=0 -mcpu=gfx1100 < %s | FileCheck -check-prefixes=CHECK %s
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define amdgpu_kernel void @icmp_test() {
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; CHECK-LABEL: icmp_test:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: v_cmp_eq_u16_e64 s[0:1], 0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: s_cmp_eq_u64 s[0:1], 0
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; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
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; CHECK-NEXT: ds_store_b32 v1, v0
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; CHECK-NEXT: s_endpgm
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entry:
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%icmp.intr = tail call i64 @llvm.amdgcn.icmp.i64.i16(i16 0, i16 0, i32 32)
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%cmp0 = icmp eq i64 %icmp.intr, 0
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%zext0 = zext i1 %cmp0 to i32
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store i32 %zext0, ptr addrspace(3) zeroinitializer, align 2147483648
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ret void
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}
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define amdgpu_kernel void @fcmp_test(half %x, half %y) {
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; CHECK-LABEL: fcmp_test:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_load_b32 s0, s[4:5], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_lshr_b32 s1, s0, 16
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
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; CHECK-NEXT: v_cmp_le_f16_e64 s[0:1], s0, s1
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; CHECK-NEXT: s_cmp_eq_u64 s[0:1], 0
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; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
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; CHECK-NEXT: ds_store_b32 v1, v0
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; CHECK-NEXT: s_endpgm
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entry:
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%fcmp.intr = tail call i64 @llvm.amdgcn.fcmp.i64.f16(half %x, half %y, i32 5)
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%cmp0 = icmp eq i64 %fcmp.intr, 0
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%zext0 = zext i1 %cmp0 to i32
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store i32 %zext0, ptr addrspace(3) zeroinitializer, align 2147483648
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ret void
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}
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define amdgpu_kernel void @ballot_test(half %x, half %y) {
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; CHECK-LABEL: ballot_test:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_b32 s0, s[4:5], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_lshr_b32 s1, s0, 16
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; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; CHECK-NEXT: v_cmp_eq_f16_e64 s[0:1], s0, s1
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; CHECK-NEXT: v_mov_b32_e32 v1, s1
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; CHECK-NEXT: ds_store_b64 v2, v[0:1]
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; CHECK-NEXT: s_endpgm
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%cmp = fcmp oeq half %x, %y
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%ballot = tail call i64 @llvm.amdgcn.ballot.i64(i1 %cmp)
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store i64 %ballot, ptr addrspace(3) zeroinitializer, align 2147483648
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ret void
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}
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declare i64 @llvm.amdgcn.icmp.i64.i16(i16, i16, i32 immarg) #0
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declare i64 @llvm.amdgcn.fcmp.i64.f16(half, half, i32 immarg) #0
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declare i64 @llvm.amdgcn.ballot.i64(i1) #0
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attributes #0 = { convergent nounwind readnone willreturn }
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