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70 lines
3.2 KiB
YAML
70 lines
3.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# Test: fixVcmpxPermlaneHazards + S_SET_VGPR_MSB interaction on GFX1250
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#
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# Proves that VGPR lowering MUST run AFTER the hazard recognizer.
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#
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# fixVcmpxPermlaneHazards creates V_MOV_B32 Reg, Reg using permlane's src0.
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# When src0 is a high VGPR (>= v256) but vdst is a low VGPR, the V_MOV_B32
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# needs {dst=1, src0=1} MSB mode, while the permlane needs {dst=0, src0=1}.
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#
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# Current order (hazard-rec then vgpr-lowering): VGPR lowering sees the
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# V_MOV_B32 and inserts S_SET_VGPR_MSB with correct {dst=1, src0=1}.
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#
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# Reversed order (vgpr-lowering then hazard-rec): The V_MOV_B32 inherits the
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# permlane's {dst=0, src0=1}, causing it to write to v44 instead of v300.
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=post-RA-hazard-rec,amdgpu-lower-vgpr-encoding -o - %s | FileCheck %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -start-before=post-RA-hazard-rec -o - %s | FileCheck -check-prefix=ASM %s
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# vcmpx + permlane with high VGPR src0 ($vgpr300) and low VGPR vdst ($vgpr0).
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# fixVcmpxPermlaneHazards inserts V_MOV_B32 $vgpr300, $vgpr300 before permlane.
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#
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# With correct order (hazard-rec then vgpr-lowering), VGPR lowering sees the
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# V_MOV_B32 and inserts S_SET_VGPR_MSB 65 {dst=1, src0=1} before it,
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# then S_SET_VGPR_MSB {dst=0, src0=1} before the permlane.
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#
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# If the order were reversed (vgpr-lowering then hazard-rec), VGPR lowering
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# would only see the permlane and insert S_SET_VGPR_MSB 1 {dst=0, src0=1}.
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# The V_MOV_B32 inserted later by the hazard recognizer would inherit dst=0,
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# writing to v44 (300 & 0xFF) instead of v300.
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#
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# ASM-LABEL: vcmpx_permlane_high_vgpr_src0:
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# ASM: v_cmpx_le_f32_e32 0, v0
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# ASM: s_set_vgpr_msb 0x41
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# ASM-NEXT: v_mov_b32_e32 v44 /*v300*/, v44 /*v300*/
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# ASM-NEXT: s_set_vgpr_msb 0x4101
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# ASM: v_permlane16_b32 v0, v44 /*v300*/, s1, s0
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---
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name: vcmpx_permlane_high_vgpr_src0
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: vcmpx_permlane_high_vgpr_src0
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: liveins: $vgpr0, $vgpr300, $sgpr0, $sgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_SET_VGPR_MSB 65, implicit-def $mode
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; CHECK-NEXT: $vgpr300 = V_MOV_B32_e32 killed $vgpr300, implicit $exec
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; CHECK-NEXT: S_SET_VGPR_MSB 16641, implicit-def $mode
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; CHECK-NEXT: $vgpr0 = V_PERMLANE16_B32_e64 0, killed $vgpr300, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr0, 0, implicit $exec
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; CHECK-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1
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liveins: $vgpr0
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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V_CMPX_LE_F32_nosdst_e32 0, $vgpr0, implicit-def $exec, implicit $mode, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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liveins: $vgpr0, $vgpr300, $sgpr0, $sgpr1
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$vgpr0 = V_PERMLANE16_B32_e64 0, killed $vgpr300, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr0, 0, implicit $exec
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S_ENDPGM 0
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...
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