derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
497 lines
19 KiB
LLVM
497 lines
19 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx802 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GFX8 %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-back-off-barrier -asm-verbose=0 < %s | FileCheck -check-prefix=GCN %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-back-off-barrier -asm-verbose=0 < %s | FileCheck -check-prefix=GCN %s
|
|
|
|
define amdgpu_kernel void @barrier_vmcnt_global(ptr addrspace(1) %arg) {
|
|
; GFX8-LABEL: barrier_vmcnt_global:
|
|
; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v2, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: s_barrier
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: barrier_vmcnt_global:
|
|
; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_barrier
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] offset:4
|
|
; GFX9-NEXT: s_endpgm
|
|
bb:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tmp1 = zext i32 %tmp to i64
|
|
%tmp2 = shl nuw nsw i64 %tmp1, 32
|
|
%tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp1
|
|
%tmp4 = load i32, ptr addrspace(1) %tmp3, align 4
|
|
fence syncscope("singlethread") release
|
|
tail call void @llvm.amdgcn.s.barrier()
|
|
fence syncscope("singlethread") acquire
|
|
%tmp5 = add nuw nsw i64 %tmp2, 4294967296
|
|
%tmp6 = lshr exact i64 %tmp5, 32
|
|
%tmp7 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp6
|
|
store i32 %tmp4, ptr addrspace(1) %tmp7, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @barrier_vscnt_global(ptr addrspace(1) %arg) {
|
|
; GFX8-LABEL: barrier_vscnt_global:
|
|
; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v3, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v3
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v3
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 1
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: s_barrier
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: barrier_vscnt_global:
|
|
; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] offset:8
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_barrier
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] offset:4
|
|
; GFX9-NEXT: s_endpgm
|
|
bb:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tmp1 = zext i32 %tmp to i64
|
|
%tmp2 = shl nuw nsw i64 %tmp1, 32
|
|
%tmp3 = add nuw nsw i64 %tmp2, 8589934592
|
|
%tmp4 = lshr exact i64 %tmp3, 32
|
|
%tmp5 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp4
|
|
store i32 0, ptr addrspace(1) %tmp5, align 4
|
|
fence syncscope("singlethread") release
|
|
tail call void @llvm.amdgcn.s.barrier()
|
|
fence syncscope("singlethread") acquire
|
|
%tmp6 = add nuw nsw i64 %tmp2, 4294967296
|
|
%tmp7 = lshr exact i64 %tmp6, 32
|
|
%tmp8 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp7
|
|
store i32 1, ptr addrspace(1) %tmp8, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @barrier_vmcnt_vscnt_global(ptr addrspace(1) %arg) {
|
|
; GFX8-LABEL: barrier_vmcnt_vscnt_global:
|
|
; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v5, 0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v4, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[2:3], v5
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: s_barrier
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v4
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: barrier_vmcnt_vscnt_global:
|
|
; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: global_store_dword v0, v2, s[0:1] offset:8
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_barrier
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] offset:4
|
|
; GFX9-NEXT: s_endpgm
|
|
bb:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tmp1 = zext i32 %tmp to i64
|
|
%tmp2 = shl nuw nsw i64 %tmp1, 32
|
|
%tmp3 = add nuw nsw i64 %tmp2, 8589934592
|
|
%tmp4 = lshr exact i64 %tmp3, 32
|
|
%tmp5 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp4
|
|
store i32 0, ptr addrspace(1) %tmp5, align 4
|
|
%tmp6 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp1
|
|
%tmp7 = load i32, ptr addrspace(1) %tmp6, align 4
|
|
fence syncscope("singlethread") release
|
|
tail call void @llvm.amdgcn.s.barrier()
|
|
fence syncscope("singlethread") acquire
|
|
%tmp8 = add nuw nsw i64 %tmp2, 4294967296
|
|
%tmp9 = lshr exact i64 %tmp8, 32
|
|
%tmp10 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp9
|
|
store i32 %tmp7, ptr addrspace(1) %tmp10, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @barrier_vmcnt_flat(ptr %arg) {
|
|
; GFX8-LABEL: barrier_vmcnt_flat:
|
|
; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v2, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX8-NEXT: s_barrier
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: barrier_vmcnt_flat:
|
|
; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: flat_load_dword v2, v[0:1]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_barrier
|
|
; GFX9-NEXT: flat_store_dword v[0:1], v2 offset:4
|
|
; GFX9-NEXT: s_endpgm
|
|
bb:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tmp1 = zext i32 %tmp to i64
|
|
%tmp2 = shl nuw nsw i64 %tmp1, 32
|
|
%tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp1
|
|
%tmp4 = load i32, ptr %tmp3, align 4
|
|
fence syncscope("singlethread") release
|
|
tail call void @llvm.amdgcn.s.barrier()
|
|
fence syncscope("singlethread") acquire
|
|
%tmp5 = add nuw nsw i64 %tmp2, 4294967296
|
|
%tmp6 = lshr exact i64 %tmp5, 32
|
|
%tmp7 = getelementptr inbounds i32, ptr %arg, i64 %tmp6
|
|
store i32 %tmp4, ptr %tmp7, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @barrier_vscnt_flat(ptr %arg) {
|
|
; GFX8-LABEL: barrier_vscnt_flat:
|
|
; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v3, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v3
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v3
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 1
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX8-NEXT: s_barrier
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: barrier_vscnt_flat:
|
|
; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 4, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: flat_store_dword v[0:1], v2 offset:4
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_barrier
|
|
; GFX9-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX9-NEXT: s_endpgm
|
|
bb:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tmp1 = zext i32 %tmp to i64
|
|
%tmp2 = shl nuw nsw i64 %tmp1, 32
|
|
%tmp3 = add nuw nsw i64 %tmp2, 8589934592
|
|
%tmp4 = lshr exact i64 %tmp3, 32
|
|
%tmp5 = getelementptr inbounds i32, ptr %arg, i64 %tmp4
|
|
store i32 0, ptr %tmp5, align 4
|
|
fence syncscope("singlethread") release
|
|
tail call void @llvm.amdgcn.s.barrier()
|
|
fence syncscope("singlethread") acquire
|
|
%tmp6 = add nuw nsw i64 %tmp2, 4294967296
|
|
%tmp7 = lshr exact i64 %tmp6, 32
|
|
%tmp8 = getelementptr inbounds i32, ptr %arg, i64 %tmp7
|
|
store i32 1, ptr %tmp8, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @barrier_vmcnt_vscnt_flat(ptr %arg) {
|
|
; GFX8-LABEL: barrier_vmcnt_vscnt_flat:
|
|
; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v5, 0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v4, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[2:3], v5
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX8-NEXT: s_barrier
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v4
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: barrier_vmcnt_vscnt_flat:
|
|
; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: flat_load_dword v2, v[0:1]
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 4, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: flat_store_dword v[0:1], v3 offset:4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_barrier
|
|
; GFX9-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX9-NEXT: s_endpgm
|
|
bb:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tmp1 = zext i32 %tmp to i64
|
|
%tmp2 = shl nuw nsw i64 %tmp1, 32
|
|
%tmp3 = add nuw nsw i64 %tmp2, 8589934592
|
|
%tmp4 = lshr exact i64 %tmp3, 32
|
|
%tmp5 = getelementptr inbounds i32, ptr %arg, i64 %tmp4
|
|
store i32 0, ptr %tmp5, align 4
|
|
%tmp6 = getelementptr inbounds i32, ptr %arg, i64 %tmp1
|
|
%tmp7 = load i32, ptr %tmp6, align 4
|
|
fence syncscope("singlethread") release
|
|
tail call void @llvm.amdgcn.s.barrier()
|
|
fence syncscope("singlethread") acquire
|
|
%tmp8 = add nuw nsw i64 %tmp2, 4294967296
|
|
%tmp9 = lshr exact i64 %tmp8, 32
|
|
%tmp10 = getelementptr inbounds i32, ptr %arg, i64 %tmp9
|
|
store i32 %tmp7, ptr %tmp10, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @barrier_vmcnt_vscnt_flat_workgroup(ptr %arg) {
|
|
; GFX8-LABEL: barrier_vmcnt_vscnt_flat_workgroup:
|
|
; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: v_mov_b32_e32 v5, 0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v4, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_store_dword v[2:3], v5
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX8-NEXT: s_barrier
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v4
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: barrier_vmcnt_vscnt_flat_workgroup:
|
|
; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: flat_load_dword v2, v[0:1]
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 4, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: flat_store_dword v[0:1], v3 offset:4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_barrier
|
|
; GFX9-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX9-NEXT: s_endpgm
|
|
bb:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tmp1 = zext i32 %tmp to i64
|
|
%tmp2 = shl nuw nsw i64 %tmp1, 32
|
|
%tmp3 = add nuw nsw i64 %tmp2, 8589934592
|
|
%tmp4 = lshr exact i64 %tmp3, 32
|
|
%tmp5 = getelementptr inbounds i32, ptr %arg, i64 %tmp4
|
|
store i32 0, ptr %tmp5, align 4
|
|
%tmp6 = getelementptr inbounds i32, ptr %arg, i64 %tmp1
|
|
%tmp7 = load i32, ptr %tmp6, align 4
|
|
fence syncscope("workgroup") release
|
|
tail call void @llvm.amdgcn.s.barrier()
|
|
fence syncscope("workgroup") acquire
|
|
%tmp8 = add nuw nsw i64 %tmp2, 4294967296
|
|
%tmp9 = lshr exact i64 %tmp8, 32
|
|
%tmp10 = getelementptr inbounds i32, ptr %arg, i64 %tmp9
|
|
store i32 %tmp7, ptr %tmp10, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @load_vmcnt_global(ptr addrspace(1) %arg) {
|
|
; GFX8-LABEL: load_vmcnt_global:
|
|
; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v2, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: load_vmcnt_global:
|
|
; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[0:1]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] offset:4
|
|
; GFX9-NEXT: s_endpgm
|
|
bb:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tmp1 = zext i32 %tmp to i64
|
|
%tmp2 = shl nuw nsw i64 %tmp1, 32
|
|
%tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp1
|
|
%tmp4 = load i32, ptr addrspace(1) %tmp3, align 4
|
|
%tmp5 = add nuw nsw i64 %tmp2, 4294967296
|
|
%tmp6 = lshr exact i64 %tmp5, 32
|
|
%tmp7 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp6
|
|
store i32 %tmp4, ptr addrspace(1) %tmp7, align 4
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @load_vmcnt_flat(ptr %arg) {
|
|
; GFX8-LABEL: load_vmcnt_flat:
|
|
; GFX8: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: flat_load_dword v2, v[0:1]
|
|
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v0
|
|
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_endpgm
|
|
;
|
|
; GFX9-LABEL: load_vmcnt_flat:
|
|
; GFX9: s_load_dwordx2 s[0:1], s[4:5], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s1
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: flat_load_dword v2, v[0:1]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: flat_store_dword v[0:1], v2 offset:4
|
|
; GFX9-NEXT: s_endpgm
|
|
bb:
|
|
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
|
%tmp1 = zext i32 %tmp to i64
|
|
%tmp2 = shl nuw nsw i64 %tmp1, 32
|
|
%tmp3 = getelementptr inbounds i32, ptr %arg, i64 %tmp1
|
|
%tmp4 = load i32, ptr %tmp3, align 4
|
|
%tmp5 = add nuw nsw i64 %tmp2, 4294967296
|
|
%tmp6 = lshr exact i64 %tmp5, 32
|
|
%tmp7 = getelementptr inbounds i32, ptr %arg, i64 %tmp6
|
|
store i32 %tmp4, ptr %tmp7, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @store_vscnt_private(ptr addrspace(5) %p) {
|
|
; GFX8-LABEL: store_vscnt_private:
|
|
; GFX8: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX8-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: store_vscnt_private:
|
|
; GFX9: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
store i32 0, ptr addrspace(5) %p
|
|
ret void
|
|
}
|
|
|
|
define void @store_vscnt_global(ptr addrspace(1) %p) {
|
|
; GFX8-LABEL: store_vscnt_global:
|
|
; GFX8: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX8-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: store_vscnt_global:
|
|
; GFX9: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: global_store_dword v[0:1], v2, off
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
store i32 0, ptr addrspace(1) %p
|
|
ret void
|
|
}
|
|
|
|
define void @store_vscnt_flat(ptr %p) {
|
|
; GFX8-LABEL: store_vscnt_flat:
|
|
; GFX8: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX8-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX8-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX8-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: store_vscnt_flat:
|
|
; GFX9: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX9-NEXT: flat_store_dword v[0:1], v2
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
store i32 0, ptr %p
|
|
ret void
|
|
}
|
|
|
|
define void @function_prologue() {
|
|
; GCN-LABEL: function_prologue:
|
|
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.amdgcn.s.barrier()
|
|
declare i32 @llvm.amdgcn.workitem.id.x()
|