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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -O0 -mtriple arm-- -mattr=+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
define void @test_fadd_s32() { ret void }
define void @test_fadd_s64() { ret void }
define void @test_fsub_s32() { ret void }
define void @test_fsub_s64() { ret void }
define void @test_fmul_s32() { ret void }
define void @test_fmul_s64() { ret void }
define void @test_fdiv_s32() { ret void }
define void @test_fdiv_s64() { ret void }
define void @test_fneg_s32() { ret void }
define void @test_fneg_s64() { ret void }
define void @test_fma_s32() { ret void }
define void @test_fma_s64() { ret void }
define void @test_fpext_s32_to_s64() { ret void }
define void @test_fptrunc_s64_to_s32() {ret void }
define void @test_fptosi_s32() { ret void }
define void @test_fptosi_s64() { ret void }
define void @test_fptoui_s32() { ret void }
define void @test_fptoui_s64() { ret void }
define void @test_sitofp_s32() { ret void }
define void @test_sitofp_s64() { ret void }
define void @test_uitofp_s32() { ret void }
define void @test_uitofp_s64() { ret void }
define void @test_load_f32() { ret void }
define void @test_load_f64() { ret void }
define void @test_stores() { ret void }
define void @test_phi_s64() { ret void }
define void @test_soft_fp_double() { ret void }
...
---
name: test_fadd_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
; CHECK-LABEL: name: test_fadd_s32
; CHECK: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK-NEXT: [[VADDS:%[0-9]+]]:spr = nofpexcept VADDS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VADDS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FADD %0, %1
$s0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $s0
...
---
name: test_fadd_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: test_fadd_s64
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK-NEXT: [[VADDD:%[0-9]+]]:dpr = nofpexcept VADDD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VADDD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FADD %0, %1
$d0 = COPY %2(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_fsub_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
; CHECK-LABEL: name: test_fsub_s32
; CHECK: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK-NEXT: [[VSUBS:%[0-9]+]]:spr = nofpexcept VSUBS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VSUBS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FSUB %0, %1
$s0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $s0
...
---
name: test_fsub_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: test_fsub_s64
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK-NEXT: [[VSUBD:%[0-9]+]]:dpr = nofpexcept VSUBD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VSUBD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FSUB %0, %1
$d0 = COPY %2(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_fmul_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
; CHECK-LABEL: name: test_fmul_s32
; CHECK: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK-NEXT: [[VMULS:%[0-9]+]]:spr = nofpexcept VMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VMULS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FMUL %0, %1
$s0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $s0
...
---
name: test_fmul_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: test_fmul_s64
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK-NEXT: [[VMULD:%[0-9]+]]:dpr = nofpexcept VMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VMULD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FMUL %0, %1
$d0 = COPY %2(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_fdiv_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $s0, $s1
; CHECK-LABEL: name: test_fdiv_s32
; CHECK: liveins: $s0, $s1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK-NEXT: [[VDIVS:%[0-9]+]]:spr = nofpexcept VDIVS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VDIVS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = G_FDIV %0, %1
$s0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $s0
...
---
name: test_fdiv_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0, $d1
; CHECK-LABEL: name: test_fdiv_s64
; CHECK: liveins: $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK-NEXT: [[VDIVD:%[0-9]+]]:dpr = nofpexcept VDIVD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VDIVD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = G_FDIV %0, %1
$d0 = COPY %2(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_fneg_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: test_fneg_s32
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK-NEXT: [[VNEGS:%[0-9]+]]:spr = VNEGS [[COPY]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $s0 = COPY [[VNEGS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0
%1(s32) = G_FNEG %0
$s0 = COPY %1(s32)
BX_RET 14, $noreg, implicit $s0
...
---
name: test_fneg_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_fneg_s64
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK-NEXT: [[VNEGD:%[0-9]+]]:dpr = VNEGD [[COPY]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $d0 = COPY [[VNEGD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0
%1(s64) = G_FNEG %0
$d0 = COPY %1(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_fma_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
- { id: 3, class: fprb }
body: |
bb.0:
liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_fma_s32
; CHECK: liveins: $s0, $s1, $s2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:spr = COPY $s2
; CHECK-NEXT: [[VFMAS:%[0-9]+]]:spr = nofpexcept VFMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VFMAS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $s0
%1(s32) = COPY $s1
%2(s32) = COPY $s2
%3(s32) = G_FMA %0, %1, %2
$s0 = COPY %3(s32)
BX_RET 14, $noreg, implicit $s0
...
---
name: test_fma_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
- { id: 3, class: fprb }
body: |
bb.0:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_fma_s64
; CHECK: liveins: $d0, $d1, $d2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:dpr = COPY $d1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:dpr = COPY $d2
; CHECK-NEXT: [[VFMAD:%[0-9]+]]:dpr = nofpexcept VFMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VFMAD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s64) = COPY $d0
%1(s64) = COPY $d1
%2(s64) = COPY $d2
%3(s64) = G_FMA %0, %1, %2
$d0 = COPY %3(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_fpext_s32_to_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: test_fpext_s32_to_s64
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK-NEXT: [[VCVTDS:%[0-9]+]]:dpr = nofpexcept VCVTDS [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $d0 = COPY [[VCVTDS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s32) = COPY $s0
%1(s64) = G_FPEXT %0(s32)
$d0 = COPY %1(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_fptrunc_s64_to_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_fptrunc_s64_to_s32
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK-NEXT: [[VCVTSD:%[0-9]+]]:spr = nofpexcept VCVTSD [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr_rm
; CHECK-NEXT: $s0 = COPY [[VCVTSD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s64) = COPY $d0
%1(s32) = G_FPTRUNC %0(s64)
$s0 = COPY %1(s32)
BX_RET 14, $noreg, implicit $s0
...
---
name: test_fptosi_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: test_fptosi_s32
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK-NEXT: [[VTOSIZS:%[0-9]+]]:spr = nofpexcept VTOSIZS [[COPY]], 14 /* CC::al */, $noreg
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]
; CHECK-NEXT: $r0 = COPY [[COPY1]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0
%1(s32) = G_FPTOSI %0(s32)
$r0 = COPY %1(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptosi_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_fptosi_s64
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK-NEXT: [[VTOSIZD:%[0-9]+]]:spr = nofpexcept VTOSIZD [[COPY]], 14 /* CC::al */, $noreg
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZD]]
; CHECK-NEXT: $r0 = COPY [[COPY1]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0
%1(s32) = G_FPTOSI %0(s64)
$r0 = COPY %1(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $s0
; CHECK-LABEL: name: test_fptoui_s32
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:spr = COPY $s0
; CHECK-NEXT: [[VTOUIZS:%[0-9]+]]:spr = nofpexcept VTOUIZS [[COPY]], 14 /* CC::al */, $noreg
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOUIZS]]
; CHECK-NEXT: $r0 = COPY [[COPY1]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s32) = COPY $s0
%1(s32) = G_FPTOUI %0(s32)
$r0 = COPY %1(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_fptoui_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: fprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: test_fptoui_s64
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr = COPY $d0
; CHECK-NEXT: [[VTOUIZD:%[0-9]+]]:spr = nofpexcept VTOUIZD [[COPY]], 14 /* CC::al */, $noreg
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOUIZD]]
; CHECK-NEXT: $r0 = COPY [[COPY1]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
%0(s64) = COPY $d0
%1(s32) = G_FPTOUI %0(s64)
$r0 = COPY %1(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_sitofp_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_sitofp_s32
; CHECK: liveins: $r0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]]
; CHECK-NEXT: [[VSITOS:%[0-9]+]]:spr = nofpexcept VSITOS [[COPY1]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $s0 = COPY [[VSITOS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $r0
%1(s32) = G_SITOFP %0(s32)
$s0 = COPY %1(s32)
BX_RET 14, $noreg, implicit $s0
...
---
name: test_sitofp_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_sitofp_s64
; CHECK: liveins: $r0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]]
; CHECK-NEXT: [[VSITOD:%[0-9]+]]:dpr = nofpexcept VSITOD [[COPY1]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $d0 = COPY [[VSITOD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s32) = COPY $r0
%1(s64) = G_SITOFP %0(s32)
$d0 = COPY %1(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_uitofp_s32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_uitofp_s32
; CHECK: liveins: $r0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]]
; CHECK-NEXT: [[VUITOS:%[0-9]+]]:spr = nofpexcept VUITOS [[COPY1]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $s0 = COPY [[VUITOS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(s32) = COPY $r0
%1(s32) = G_UITOFP %0(s32)
$s0 = COPY %1(s32)
BX_RET 14, $noreg, implicit $s0
...
---
name: test_uitofp_s64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_uitofp_s64
; CHECK: liveins: $r0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]]
; CHECK-NEXT: [[VUITOD:%[0-9]+]]:dpr = nofpexcept VUITOD [[COPY1]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $d0 = COPY [[VUITOD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(s32) = COPY $r0
%1(s64) = G_UITOFP %0(s32)
$d0 = COPY %1(s64)
BX_RET 14, $noreg, implicit $d0
...
---
name: test_load_f32
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_load_f32
; CHECK: liveins: $r0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK-NEXT: [[VLDRS:%[0-9]+]]:spr = VLDRS [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32))
; CHECK-NEXT: $s0 = COPY [[VLDRS]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $s0
%0(p0) = COPY $r0
%1(s32) = G_LOAD %0(p0) :: (load (s32))
$s0 = COPY %1
BX_RET 14, $noreg, implicit $s0
...
---
name: test_load_f64
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
body: |
bb.0:
liveins: $r0
; CHECK-LABEL: name: test_load_f64
; CHECK: liveins: $r0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK-NEXT: [[VLDRD:%[0-9]+]]:dpr = VLDRD [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s64))
; CHECK-NEXT: $d0 = COPY [[VLDRD]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0
%0(p0) = COPY $r0
%1(s64) = G_LOAD %0(p0) :: (load (s64))
$d0 = COPY %1
BX_RET 14, $noreg, implicit $d0
...
---
name: test_stores
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: fprb }
- { id: 2, class: fprb }
body: |
bb.0:
liveins: $r0, $s0, $d0
; CHECK-LABEL: name: test_stores
; CHECK: liveins: $r0, $s0, $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY $s0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:dpr = COPY $d2
; CHECK-NEXT: VSTRS [[COPY1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))
; CHECK-NEXT: VSTRD [[COPY2]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s64))
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg
%0(p0) = COPY $r0
%1(s32) = COPY $s0
%2(s64) = COPY $d2
G_STORE %1(s32), %0(p0) :: (store (s32))
G_STORE %2(s64), %0(p0) :: (store (s64))
BX_RET 14, $noreg
...
---
name: test_phi_s64
# CHECK-LABEL: name: test_phi_s64
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: fprb }
- { id: 3, class: fprb }
- { id: 4, class: fprb }
body: |
bb.0:
; CHECK: [[BB1:bb.0]]:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $d0, $d1
%0(s32) = COPY $r0
%1(s1) = G_TRUNC %0(s32)
%2(s64) = COPY $d0
%3(s64) = COPY $d1
; CHECK: [[V1:%[0-9]+]]:dpr = COPY $d0
; CHECK: [[V2:%[0-9]+]]:dpr = COPY $d1
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
bb.1:
; CHECK: [[BB2:bb.1]]:
successors: %bb.2(0x80000000)
G_BR %bb.2
; CHECK: B %bb.2
bb.2:
; CHECK: bb.2
%4(s64) = G_PHI %2(s64), %bb.0, %3(s64), %bb.1
; CHECK: {{%[0-9]+}}:dpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]]
$d0 = COPY %4(s64)
BX_RET 14 /* CC::al */, $noreg, implicit $d0
...
---
name: test_soft_fp_double
legalized: true
regBankSelected: true
selected: false
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: fprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
body: |
bb.0:
liveins: $r0, $r1, $r2, $r3
; CHECK-LABEL: name: test_soft_fp_double
; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $r2
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r3
; CHECK-NEXT: [[VMOVDRR:%[0-9]+]]:dpr = VMOVDRR [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
; CHECK-NEXT: [[VMOVRRD:%[0-9]+]]:gpr, [[VMOVRRD1:%[0-9]+]]:gpr = VMOVRRD [[VMOVDRR]], 14 /* CC::al */, $noreg
; CHECK-NEXT: $r0 = COPY [[VMOVRRD]]
; CHECK-NEXT: $r1 = COPY [[VMOVRRD1]]
; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1
%0(s32) = COPY $r2
%1(s32) = COPY $r3
%2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
%3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64)
$r0 = COPY %3
$r1 = COPY %4
BX_RET 14, $noreg, implicit $r0, implicit $r1
...
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