derek.holloway
7502bf64a4
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47 lines
1.4 KiB
LLVM
47 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
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; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-CMP
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; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-BX
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define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK-LABEL: t1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: cmp r2, #1
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; CHECK-NEXT: cmpne r2, #7
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; CHECK-NEXT: addne r0, r1, r0
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; CHECK-NEXT: addeq r0, r0, r1
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; CHECK-NEXT: addeq r0, r0, #1
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; CHECK-NEXT: bx lr
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;
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; CHECK-V4-CMP-LABEL: t1:
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; CHECK-V4-CMP: @ %bb.0:
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; CHECK-V4-CMP-NEXT: cmp r2, #7
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; CHECK-V4-CMP-NEXT: cmpne r2, #1
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; CHECK-V4-CMP-NEXT: addne r0, r1, r0
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; CHECK-V4-CMP-NEXT: addeq r0, r0, r1
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; CHECK-V4-CMP-NEXT: addeq r0, r0, #1
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; CHECK-V4-CMP-NEXT: bx lr
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;
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; CHECK-V4-BX-LABEL: t1:
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; CHECK-V4-BX: @ %bb.0:
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; CHECK-V4-BX-NEXT: cmp r2, #7
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; CHECK-V4-BX-NEXT: cmpne r2, #1
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; CHECK-V4-BX-NEXT: addne r0, r1, r0
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; CHECK-V4-BX-NEXT: addeq r0, r0, r1
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; CHECK-V4-BX-NEXT: addeq r0, r0, #1
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; CHECK-V4-BX-NEXT: bx lr
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switch i32 %c, label %cond_next [
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i32 1, label %cond_true
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i32 7, label %cond_true
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]
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cond_true:
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%tmp12 = add i32 %a, 1
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%tmp1518 = add i32 %tmp12, %b
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ret i32 %tmp1518
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cond_next:
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%tmp15 = add i32 %b, %a
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ret i32 %tmp15
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}
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