derek.holloway
7502bf64a4
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107 lines
3.3 KiB
LLVM
107 lines
3.3 KiB
LLVM
; RUN: llc -mtriple armv7-linux -mattr=+neon %s -o - | FileCheck %s --check-prefix=LE
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; RUN: llc -mtriple armebv7-linux -mattr=+neon %s -o - | FileCheck %s --check-prefix=BE
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; The key is the last vrev64 should be vrev64.16 instead of vrev64.32
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define void @sdiv_shl(ptr %x, ptr %y) nounwind {
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; LE-LABEL: sdiv_shl:
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; LE: @ %bb.0: @ %entry
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; LE-NEXT: adr r2, .LCPI0_0
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; LE-NEXT: vld1.64 {d18, d19}, [r1]
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; LE-NEXT: adr r1, .LCPI0_1
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; LE-NEXT: vld1.64 {d16, d17}, [r2:128]
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; LE-NEXT: vshr.s16 q10, q9, #15
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; LE-NEXT: vneg.s16 q8, q8
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; LE-NEXT: vld1.64 {d22, d23}, [r1:128]
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; LE-NEXT: adr r1, .LCPI0_2
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; LE-NEXT: vshl.u16 q8, q10, q8
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; LE-NEXT: vneg.s16 q10, q11
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; LE-NEXT: vadd.i16 q8, q9, q8
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; LE-NEXT: vshl.s16 q8, q8, q10
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; LE-NEXT: vld1.64 {d20, d21}, [r1:128]
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; LE-NEXT: vbit q8, q9, q10
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; LE-NEXT: vst1.64 {d16, d17}, [r0]
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; LE: .LCPI0_0:
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; LE-NEXT: .short 16 @ 0x10
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; LE-NEXT: .short 14 @ 0xe
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; LE-NEXT: .short 15 @ 0xf
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; LE-NEXT: .short 13 @ 0xd
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; LE-NEXT: .short 12 @ 0xc
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; LE-NEXT: .short 10 @ 0xa
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; LE-NEXT: .short 11 @ 0xb
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; LE-NEXT: .short 9 @ 0x9
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; LE-NEXT: .LCPI0_1:
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; LE-NEXT: .short 0 @ 0x0
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; LE-NEXT: .short 2 @ 0x2
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; LE-NEXT: .short 1 @ 0x1
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; LE-NEXT: .short 3 @ 0x3
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; LE-NEXT: .short 4 @ 0x4
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; LE-NEXT: .short 6 @ 0x6
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; LE-NEXT: .short 5 @ 0x5
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; LE-NEXT: .short 7 @ 0x7
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; LE-NEXT: .LCPI0_2:
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; LE-NEXT: .short 65535 @ 0xffff
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; LE-NEXT: .short 0 @ 0x0
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; LE-NEXT: .short 0 @ 0x0
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; LE-NEXT: .short 0 @ 0x0
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; LE-NEXT: .short 0 @ 0x0
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; LE-NEXT: .short 0 @ 0x0
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; LE-NEXT: .short 0 @ 0x0
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; LE-NEXT: .short 0 @ 0x0
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;
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; BE-LABEL: sdiv_shl:
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; BE: @ %bb.0: @ %entry
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; BE-NEXT: adr r2, .LCPI0_0
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; BE-NEXT: vld1.64 {d18, d19}, [r1]
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; BE-NEXT: adr r1, .LCPI0_1
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; BE-NEXT: vld1.64 {d16, d17}, [r2:128]
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; BE-NEXT: vrev64.16 q8, q8
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; BE-NEXT: vrev64.16 q9, q9
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; BE-NEXT: vneg.s16 q8, q8
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; BE-NEXT: vld1.64 {d20, d21}, [r1:128]
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; BE-NEXT: adr r1, .LCPI0_2
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; BE-NEXT: vshr.s16 q11, q9, #15
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; BE-NEXT: vrev64.16 q10, q10
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; BE-NEXT: vshl.u16 q8, q11, q8
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; BE-NEXT: vld1.64 {d22, d23}, [r1:128]
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; BE-NEXT: vneg.s16 q10, q10
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; BE-NEXT: vrev64.16 q11, q11
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; BE-NEXT: vadd.i16 q8, q9, q8
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; BE-NEXT: vshl.s16 q8, q8, q10
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; BE-NEXT: vbit q8, q9, q11
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; BE-NEXT: vrev64.16 q8, q8
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; BE-NEXT: vst1.64 {d16, d17}, [r0]
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; BE: .LCPI0_0:
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; BE-NEXT: .short 16 @ 0x10
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; BE-NEXT: .short 14 @ 0xe
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; BE-NEXT: .short 15 @ 0xf
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; BE-NEXT: .short 13 @ 0xd
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; BE-NEXT: .short 12 @ 0xc
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; BE-NEXT: .short 10 @ 0xa
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; BE-NEXT: .short 11 @ 0xb
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; BE-NEXT: .short 9 @ 0x9
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; BE-NEXT: .LCPI0_1:
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; BE-NEXT: .short 0 @ 0x0
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; BE-NEXT: .short 2 @ 0x2
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; BE-NEXT: .short 1 @ 0x1
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; BE-NEXT: .short 3 @ 0x3
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; BE-NEXT: .short 4 @ 0x4
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; BE-NEXT: .short 6 @ 0x6
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; BE-NEXT: .short 5 @ 0x5
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; BE-NEXT: .short 7 @ 0x7
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; BE-NEXT: .LCPI0_2:
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; BE-NEXT: .short 65535 @ 0xffff
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; BE-NEXT: .short 0 @ 0x0
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; BE-NEXT: .short 0 @ 0x0
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; BE-NEXT: .short 0 @ 0x0
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; BE-NEXT: .short 0 @ 0x0
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; BE-NEXT: .short 0 @ 0x0
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; BE-NEXT: .short 0 @ 0x0
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; BE-NEXT: .short 0 @ 0x0
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entry:
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%0 = load <8 x i16>, ptr %y, align 8
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%div = sdiv <8 x i16> %0, <i16 1, i16 4, i16 2, i16 8, i16 16, i16 64, i16 32, i16 128>
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store <8 x i16> %div, ptr %x, align 8
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ret void
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}
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