derek.holloway
7502bf64a4
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52 lines
1.4 KiB
LLVM
52 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=swift < %s | FileCheck %s
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; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC
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; Release operations only need the store barrier provided by a "dmb ishst",
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define void @test_store_release(ptr %p, i32 %v) {
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; CHECK-LABEL: test_store_release:
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; CHECK: dmb ishst
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; CHECK: str
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; CHECK-STRICT-ATOMIC-LABEL: test_store_release:
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; CHECK-STRICT-ATOMIC: dmb {{ish$}}
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store atomic i32 %v, ptr %p release, align 4
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ret void
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}
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; However, if sequential consistency is needed *something* must ensure a release
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; followed by an acquire does not get reordered. In that case a "dmb ishst" is
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; not adequate.
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define i32 @test_seq_cst(ptr %p, i32 %v) {
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; CHECK-LABEL: test_seq_cst:
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; CHECK: dmb ishst
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; CHECK: str
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; CHECK: dmb {{ish$}}
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; CHECK: ldr
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; CHECK: dmb {{ish$}}
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; CHECK-STRICT-ATOMIC-LABEL: test_seq_cst:
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; CHECK-STRICT-ATOMIC: dmb {{ish$}}
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; CHECK-STRICT-ATOMIC: str
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; CHECK-STRICT-ATOMIC: dmb {{ish$}}
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; CHECK-STRICT-ATOMIC: ldr
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; CHECK-STRICT-ATOMIC: dmb {{ish$}}
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store atomic i32 %v, ptr %p seq_cst, align 4
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%val = load atomic i32, ptr %p seq_cst, align 4
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ret i32 %val
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}
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; Also, pure acquire operations should definitely not have an ishst barrier.
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define i32 @test_acq(ptr %addr) {
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; CHECK-LABEL: test_acq:
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; CHECK: ldr
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; CHECK: dmb {{ish$}}
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; CHECK-STRICT-ATOMIC-LABEL: test_acq:
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; CHECK-STRICT-ATOMIC: dmb {{ish$}}
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%val = load atomic i32, ptr %addr acquire, align 4
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ret i32 %val
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}
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