derek.holloway
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84 lines
2.3 KiB
LLVM
84 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,ARMV6
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+dsp %s -o - | FileCheck %s --check-prefixes=CHECK,THUMB
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define arm_aapcs_vfpcc i32 @usat_lsl(i32 %num){
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; CHECK-LABEL: usat_lsl:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: usat r0, #7, r0, lsl #2
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; CHECK-NEXT: bx lr
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entry:
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%shl = shl i32 %num, 2
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%0 = tail call i32 @llvm.arm.usat(i32 %shl, i32 7)
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ret i32 %0
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}
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define arm_aapcs_vfpcc i32 @usat_asr(i32 %num){
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; CHECK-LABEL: usat_asr:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: usat r0, #7, r0, asr #2
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; CHECK-NEXT: bx lr
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entry:
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%shr = ashr i32 %num, 2
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%0 = tail call i32 @llvm.arm.usat(i32 %shr, i32 7)
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ret i32 %0
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}
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define arm_aapcs_vfpcc i32 @usat_lsl2(i32 %num){
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; ARMV6-LABEL: usat_lsl2:
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; ARMV6: @ %bb.0: @ %entry
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; ARMV6-NEXT: lsl r0, r0, #15
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; ARMV6-NEXT: bic r1, r0, r0, asr #31
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; ARMV6-NEXT: mov r0, #255
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; ARMV6-NEXT: orr r0, r0, #32512
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; ARMV6-NEXT: cmp r1, r0
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; ARMV6-NEXT: movlt r0, r1
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; ARMV6-NEXT: bx lr
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;
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; THUMB-LABEL: usat_lsl2:
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; THUMB: @ %bb.0: @ %entry
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; THUMB-NEXT: lsls r0, r0, #15
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; THUMB-NEXT: movw r1, #32767
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; THUMB-NEXT: bic.w r0, r0, r0, asr #31
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; THUMB-NEXT: cmp r0, r1
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; THUMB-NEXT: csel r0, r0, r1, lt
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; THUMB-NEXT: bx lr
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entry:
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%shl = shl nsw i32 %num, 15
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%0 = icmp sgt i32 %shl, 0
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%1 = select i1 %0, i32 %shl, i32 0
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%2 = icmp slt i32 %1, 32767
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%3 = select i1 %2, i32 %1, i32 32767
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ret i32 %3
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}
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define arm_aapcs_vfpcc i32 @usat_asr2(i32 %num){
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; ARMV6-LABEL: usat_asr2:
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; ARMV6: @ %bb.0: @ %entry
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; ARMV6-NEXT: asr r1, r0, #15
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; ARMV6-NEXT: bic r1, r1, r0, asr #31
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; ARMV6-NEXT: mov r0, #255
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; ARMV6-NEXT: orr r0, r0, #32512
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; ARMV6-NEXT: cmp r1, r0
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; ARMV6-NEXT: movlt r0, r1
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; ARMV6-NEXT: bx lr
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;
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; THUMB-LABEL: usat_asr2:
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; THUMB: @ %bb.0: @ %entry
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; THUMB-NEXT: asrs r1, r0, #15
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; THUMB-NEXT: bic.w r0, r1, r0, asr #31
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; THUMB-NEXT: movw r1, #32767
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; THUMB-NEXT: cmp r0, r1
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; THUMB-NEXT: csel r0, r0, r1, lt
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; THUMB-NEXT: bx lr
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entry:
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%shr = ashr i32 %num, 15
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%0 = icmp sgt i32 %shr, 0
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%1 = select i1 %0, i32 %shr, i32 0
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%2 = icmp slt i32 %1, 32767
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%3 = select i1 %2, i32 %1, i32 32767
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ret i32 %3
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}
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declare i32 @llvm.arm.usat(i32, i32)
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