derek.holloway
7502bf64a4
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139 lines
3.2 KiB
LLVM
139 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple armv6-- -filetype asm -o - %s | FileCheck %s
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define i32 @test1(i32 %x) {
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; CHECK-LABEL: test1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb16 r0, r0
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; CHECK-NEXT: bx lr
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%tmp1 = and i32 %x, 16711935
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ret i32 %tmp1
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}
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: test2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb16 r0, r0, ror #8
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; CHECK-NEXT: bx lr
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%tmp1 = lshr i32 %x, 8
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%tmp2 = and i32 %tmp1, 16711935
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ret i32 %tmp2
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}
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define i32 @test3(i32 %x) {
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; CHECK-LABEL: test3:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb16 r0, r0, ror #8
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; CHECK-NEXT: bx lr
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%tmp1 = lshr i32 %x, 8
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%tmp2 = and i32 %tmp1, 16711935
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ret i32 %tmp2
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}
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define i32 @test4(i32 %x) {
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; CHECK-LABEL: test4:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb16 r0, r0, ror #8
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; CHECK-NEXT: bx lr
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%tmp1 = lshr i32 %x, 8
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%tmp6 = and i32 %tmp1, 16711935
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ret i32 %tmp6
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}
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define i32 @test5(i32 %x) {
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; CHECK-LABEL: test5:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb16 r0, r0, ror #8
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; CHECK-NEXT: bx lr
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%tmp1 = lshr i32 %x, 8
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%tmp2 = and i32 %tmp1, 16711935
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ret i32 %tmp2
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}
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define i32 @test6(i32 %x) {
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; CHECK-LABEL: test6:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb16 r0, r0, ror #16
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; CHECK-NEXT: bx lr
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%tmp1 = lshr i32 %x, 16
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%tmp2 = and i32 %tmp1, 255
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%tmp4 = shl i32 %x, 16
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%tmp5 = and i32 %tmp4, 16711680
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%tmp6 = or i32 %tmp2, %tmp5
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ret i32 %tmp6
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}
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define i32 @test7(i32 %x) {
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; CHECK-LABEL: test7:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb16 r0, r0, ror #16
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; CHECK-NEXT: bx lr
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%tmp1 = lshr i32 %x, 16
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%tmp2 = and i32 %tmp1, 255
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%tmp4 = shl i32 %x, 16
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%tmp5 = and i32 %tmp4, 16711680
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%tmp6 = or i32 %tmp2, %tmp5
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ret i32 %tmp6
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}
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define i32 @test8(i32 %x) {
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; CHECK-LABEL: test8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb16 r0, r0, ror #24
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; CHECK-NEXT: bx lr
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%tmp1 = shl i32 %x, 8
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%tmp2 = and i32 %tmp1, 16711680
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%tmp5 = lshr i32 %x, 24
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%tmp6 = or i32 %tmp2, %tmp5
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ret i32 %tmp6
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}
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define i32 @test9(i32 %x) {
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; CHECK-LABEL: test9:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: uxtb16 r0, r0, ror #24
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; CHECK-NEXT: bx lr
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%tmp1 = lshr i32 %x, 24
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%tmp4 = shl i32 %x, 8
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%tmp5 = and i32 %tmp4, 16711680
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%tmp6 = or i32 %tmp5, %tmp1
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ret i32 %tmp6
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}
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; FIXME: Failed to match uxtb16
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define i32 @test10(i32 %p0) {
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; CHECK-LABEL: test10:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #248
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; CHECK-NEXT: mov r2, #7
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; CHECK-NEXT: orr r1, r1, #16252928
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; CHECK-NEXT: orr r2, r2, #458752
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; CHECK-NEXT: and r1, r1, r0, lsr #7
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; CHECK-NEXT: and r0, r2, r0, lsr #12
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; CHECK-NEXT: orr r0, r0, r1
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; CHECK-NEXT: bx lr
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%tmp1 = lshr i32 %p0, 7
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%tmp2 = and i32 %tmp1, 16253176
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%tmp4 = lshr i32 %p0, 12
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%tmp5 = and i32 %tmp4, 458759
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%tmp7 = or i32 %tmp5, %tmp2
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ret i32 %tmp7
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}
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define i32 @test11(i32 %p0) {
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; CHECK-LABEL: test11:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #1
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; CHECK-NEXT: and r0, r0, #3
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; CHECK-NEXT: orr r1, r1, #65536
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; CHECK-NEXT: lsl r0, r1, r0
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; CHECK-NEXT: lsr r0, r0, #1
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; CHECK-NEXT: uxtb16 r0, r0
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; CHECK-NEXT: bx lr
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%p = and i32 %p0, 3
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%a = shl i32 65537, %p
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%b = lshr i32 %a, 1
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%tmp7 = and i32 %b, 458759
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ret i32 %tmp7
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}
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