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44 lines
1.8 KiB
YAML
44 lines
1.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass arm-ldst-opt -verify-machineinstrs %s -o - | FileCheck %s
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# ARM load store optimizer was dealing with a sequence like:
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# s1 = VLDRS [r0, 1], implicit-def Q0
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# s3 = VLDRS [r0, 2], implicit killed Q0, implicit-def Q0
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# s0 = VLDRS [r0, 0], implicit killed Q0, implicit-def Q0
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# s2 = VLDRS [r0, 4], implicit killed Q0, implicit-def Q0
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#
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# It decided to combine the {s0, s1} loads into a single instruction in the
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# third position. However, this leaves the instruction defining s3 with a stray
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# imp-use of Q0, which is undefined.
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#
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# The verifier catches this, so this test just makes sure that appropriate
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# liveness flags are added.
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--- |
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target triple = "thumbv7-apple-ios"
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define arm_aapcs_vfpcc <4 x float> @foo(ptr %ptr) {
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ret <4 x float> undef
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}
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...
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---
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name: foo
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alignment: 2
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liveins:
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- { reg: '$r0' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $r0
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; CHECK-LABEL: name: foo
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; CHECK: $s3 = VLDRS $r0, 2, 14 /* CC::al */, $noreg, implicit killed undef $q0, implicit-def $q0 :: (load (s32))
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; CHECK: VLDMSIA $r0, 14 /* CC::al */, $noreg, def $s0, def $s1, implicit-def $noreg :: (load (s32))
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; CHECK: $s2 = VLDRS killed $r0, 4, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s32))
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
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$s1 = VLDRS $r0, 1, 14, $noreg, implicit-def $q0 :: (load (s32))
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$s3 = VLDRS $r0, 2, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s32))
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$s0 = VLDRS $r0, 0, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s32))
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$s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load (s32))
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tBX_RET 14, $noreg, implicit $q0
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...
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