derek.holloway
7502bf64a4
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201 lines
6.0 KiB
LLVM
201 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mcpu=v2 -mtriple=bpf < %s | FileCheck %s --check-prefixes=CHECK-V2
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; RUN: llc -mcpu=v4 -mtriple=bpf < %s | FileCheck %s --check-prefixes=CHECK-V4
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; Zero extension instructions should be eliminated at instruction
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; selection phase for all test cases below.
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; In BPF zero extension is implemented as &= or a pair of <<=/>>=
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; instructions, hence simply check that &= and >>= do not exist in
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; generated code (<<= remains because %c is used by both call and
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; lshr in a few test cases).
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define void @shl_lshr_same_bb(ptr %p) {
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; CHECK-V2-LABEL: shl_lshr_same_bb:
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; CHECK-V2: # %bb.0: # %entry
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; CHECK-V2-NEXT: r1 = *(u8 *)(r1 + 0)
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; CHECK-V2-NEXT: r5 = 1
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; CHECK-V2-NEXT: if r1 == 0 goto .LBB0_2
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; CHECK-V2-NEXT: # %bb.1: # %entry
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; CHECK-V2-NEXT: r5 = 0
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; CHECK-V2-NEXT: .LBB0_2: # %entry
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; CHECK-V2-NEXT: r3 = r1
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; CHECK-V2-NEXT: r3 <<= 56
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; CHECK-V2-NEXT: r2 = r1
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; CHECK-V2-NEXT: r4 = r1
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; CHECK-V2-NEXT: call sink1
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; CHECK-V2-NEXT: exit
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;
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; CHECK-V4-LABEL: shl_lshr_same_bb:
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; CHECK-V4: # %bb.0: # %entry
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; CHECK-V4-NEXT: w1 = *(u8 *)(r1 + 0)
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; CHECK-V4-NEXT: w5 = 1
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; CHECK-V4-NEXT: if w1 == 0 goto .LBB0_2
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; CHECK-V4-NEXT: # %bb.1: # %entry
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; CHECK-V4-NEXT: w5 = 0
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; CHECK-V4-NEXT: .LBB0_2: # %entry
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; CHECK-V4-NEXT: r3 = r1
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; CHECK-V4-NEXT: r3 <<= 56
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; CHECK-V4-NEXT: r2 = r1
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; CHECK-V4-NEXT: r4 = r1
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; CHECK-V4-NEXT: call sink1
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; CHECK-V4-NEXT: exit
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entry:
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%a = load i8, ptr %p, align 1
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%b = zext i8 %a to i64
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%c = shl i64 %b, 56
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%d = lshr i64 %c, 56
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%e = icmp eq i64 %d, 0
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; hasOneUse() is a common requirement for many CombineDAG
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; transofmations, make sure that it does not matter in this case.
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call void @sink1(i8 %a, i64 %b, i64 %c, i64 %d, i1 %e)
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ret void
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}
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define void @shl_lshr_diff_bb(ptr %p) {
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; CHECK-V2-LABEL: shl_lshr_diff_bb:
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; CHECK-V2: # %bb.0: # %entry
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; CHECK-V2-NEXT: r1 = *(u16 *)(r1 + 0)
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; CHECK-V2-NEXT: r5 = 1
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; CHECK-V2-NEXT: if r1 == 0 goto .LBB1_2
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; CHECK-V2-NEXT: # %bb.1: # %entry
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; CHECK-V2-NEXT: r5 = 0
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; CHECK-V2-NEXT: .LBB1_2: # %entry
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; CHECK-V2-NEXT: r3 = r1
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; CHECK-V2-NEXT: r3 <<= 48
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; CHECK-V2-NEXT: r2 = r1
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; CHECK-V2-NEXT: r4 = r1
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; CHECK-V2-NEXT: call sink2
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; CHECK-V2-NEXT: exit
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;
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; CHECK-V4-LABEL: shl_lshr_diff_bb:
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; CHECK-V4: # %bb.0: # %entry
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; CHECK-V4-NEXT: w1 = *(u16 *)(r1 + 0)
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; CHECK-V4-NEXT: w5 = 1
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; CHECK-V4-NEXT: if w1 == 0 goto .LBB1_2
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; CHECK-V4-NEXT: # %bb.1: # %entry
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; CHECK-V4-NEXT: w5 = 0
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; CHECK-V4-NEXT: .LBB1_2: # %entry
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; CHECK-V4-NEXT: r3 = r1
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; CHECK-V4-NEXT: r3 <<= 48
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; CHECK-V4-NEXT: r2 = r1
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; CHECK-V4-NEXT: r4 = r1
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; CHECK-V4-NEXT: call sink2
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; CHECK-V4-NEXT: exit
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entry:
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%a = load i16, ptr %p, align 2
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%b = zext i16 %a to i64
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%c = shl i64 %b, 48
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%d = lshr i64 %c, 48
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br label %next
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; Jump to the new basic block creates a COPY instruction for %d, which
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; might be materialized as noop or as AND_ri (zero extension) at the
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; start of the basic block. The decision depends on TLI.isZExtFree()
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; results, see RegsForValue::getCopyToRegs(). Check below verifies
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; that COPY is materialized as noop.
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next:
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%e = icmp eq i64 %d, 0
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call void @sink2(i16 %a, i64 %b, i64 %c, i64 %d, i1 %e)
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ret void
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}
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define void @load_zext_same_bb(ptr %p) {
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; CHECK-V2-LABEL: load_zext_same_bb:
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; CHECK-V2: # %bb.0: # %entry
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; CHECK-V2-NEXT: r1 = *(u8 *)(r1 + 0)
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; CHECK-V2-NEXT: r2 = 1
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; CHECK-V2-NEXT: if r1 == 0 goto .LBB2_2
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; CHECK-V2-NEXT: # %bb.1: # %entry
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; CHECK-V2-NEXT: r2 = 0
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; CHECK-V2-NEXT: .LBB2_2: # %entry
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; CHECK-V2-NEXT: call sink3
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; CHECK-V2-NEXT: exit
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;
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; CHECK-V4-LABEL: load_zext_same_bb:
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; CHECK-V4: # %bb.0: # %entry
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; CHECK-V4-NEXT: w1 = *(u8 *)(r1 + 0)
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; CHECK-V4-NEXT: w2 = 1
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; CHECK-V4-NEXT: if w1 == 0 goto .LBB2_2
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; CHECK-V4-NEXT: # %bb.1: # %entry
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; CHECK-V4-NEXT: w2 = 0
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; CHECK-V4-NEXT: .LBB2_2: # %entry
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; CHECK-V4-NEXT: call sink3
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; CHECK-V4-NEXT: exit
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entry:
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%a = load i8, ptr %p, align 1
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; zext is implicit in this context
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%b = icmp eq i8 %a, 0
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call void @sink3(i8 %a, i1 %b)
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ret void
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}
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define void @load_zext_diff_bb(ptr %p) {
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; CHECK-V2-LABEL: load_zext_diff_bb:
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; CHECK-V2: # %bb.0: # %entry
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; CHECK-V2-NEXT: r1 = *(u8 *)(r1 + 0)
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; CHECK-V2-NEXT: r2 = 1
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; CHECK-V2-NEXT: if r1 == 0 goto .LBB3_2
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; CHECK-V2-NEXT: # %bb.1: # %next
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; CHECK-V2-NEXT: r2 = 0
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; CHECK-V2-NEXT: .LBB3_2: # %next
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; CHECK-V2-NEXT: call sink3
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; CHECK-V2-NEXT: exit
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;
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; CHECK-V4-LABEL: load_zext_diff_bb:
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; CHECK-V4: # %bb.0: # %entry
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; CHECK-V4-NEXT: w1 = *(u8 *)(r1 + 0)
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; CHECK-V4-NEXT: w2 = 1
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; CHECK-V4-NEXT: if w1 == 0 goto .LBB3_2
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; CHECK-V4-NEXT: # %bb.1: # %next
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; CHECK-V4-NEXT: w2 = 0
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; CHECK-V4-NEXT: .LBB3_2: # %next
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; CHECK-V4-NEXT: call sink3
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; CHECK-V4-NEXT: exit
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entry:
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%a = load i8, ptr %p, align 1
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br label %next
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next:
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%b = icmp eq i8 %a, 0
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call void @sink3(i8 %a, i1 %b)
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ret void
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}
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define void @load_zext_diff_bb_2(ptr %p) {
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; CHECK-V2-LABEL: load_zext_diff_bb_2:
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; CHECK-V2: # %bb.0: # %entry
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; CHECK-V2-NEXT: r1 = *(u32 *)(r1 + 0)
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; CHECK-V2-NEXT: r2 = 1
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; CHECK-V2-NEXT: if r1 == 0 goto .LBB4_2
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; CHECK-V2-NEXT: # %bb.1: # %next
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; CHECK-V2-NEXT: r2 = 0
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; CHECK-V2-NEXT: .LBB4_2: # %next
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; CHECK-V2-NEXT: call sink4
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; CHECK-V2-NEXT: exit
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;
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; CHECK-V4-LABEL: load_zext_diff_bb_2:
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; CHECK-V4: # %bb.0: # %entry
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; CHECK-V4-NEXT: w1 = *(u32 *)(r1 + 0)
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; CHECK-V4-NEXT: w2 = 1
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; CHECK-V4-NEXT: if w1 == 0 goto .LBB4_2
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; CHECK-V4-NEXT: # %bb.1: # %next
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; CHECK-V4-NEXT: w2 = 0
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; CHECK-V4-NEXT: .LBB4_2: # %next
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; CHECK-V4-NEXT: call sink4
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; CHECK-V4-NEXT: exit
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entry:
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%a = load i32, ptr %p, align 4
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br label %next
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next:
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%b = icmp eq i32 %a, 0
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call void @sink4(i32 %a, i1 %b)
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ret void
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}
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declare void @sink1(i8, i64, i64, i64, i1);
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declare void @sink2(i16, i64, i64, i64, i1);
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declare void @sink3(i8, i1);
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declare void @sink4(i32, i1);
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