derek.holloway
7502bf64a4
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304 lines
7.3 KiB
LLVM
304 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF
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; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2
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define float @faddRR(float %x, float %y) {
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;
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; CHECK-SF-LABEL: faddRR:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fadds vr0, vr1, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: faddRR:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fadd.32 vr0, vr1, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fadd = fadd float %y, %x
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ret float %fadd
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}
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define float @faddRI(float %x) {
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;
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; CHECK-SF-LABEL: faddRI:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: movih32 a0, 16672
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; CHECK-SF-NEXT: fmtvrl vr1, a0
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; CHECK-SF-NEXT: fadds vr0, vr0, vr1
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: faddRI:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: movih32 a0, 16672
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; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
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; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr1
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; CHECK-SF2-NEXT: rts16
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entry:
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%fadd = fadd float %x, 10.0
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ret float %fadd
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}
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define float @faddRI_X(float %x) {
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;
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; CHECK-SF-LABEL: faddRI_X:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: movih32 a0, 17792
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; CHECK-SF-NEXT: ori32 a0, a0, 2048
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; CHECK-SF-NEXT: fmtvrl vr1, a0
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; CHECK-SF-NEXT: fadds vr0, vr0, vr1
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: faddRI_X:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: movih32 a0, 17792
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; CHECK-SF2-NEXT: ori32 a0, a0, 2048
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; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
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; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr1
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; CHECK-SF2-NEXT: rts16
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entry:
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%fadd = fadd float %x, 4097.0
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ret float %fadd
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}
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define float @fsubRR(float %x, float %y) {
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;
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; CHECK-SF-LABEL: fsubRR:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fsubs vr0, vr1, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fsubRR:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fsub.32 vr0, vr1, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fsub = fsub float %y, %x
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ret float %fsub
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}
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define float @fsubRI(float %x) {
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;
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; CHECK-SF-LABEL: fsubRI:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: movih32 a0, 49440
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; CHECK-SF-NEXT: fmtvrl vr1, a0
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; CHECK-SF-NEXT: fadds vr0, vr0, vr1
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fsubRI:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: movih32 a0, 49440
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; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
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; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr1
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; CHECK-SF2-NEXT: rts16
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entry:
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%fsub = fsub float %x, 10.0
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ret float %fsub
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}
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define float @fsubRI_X(float %x) {
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;
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; CHECK-SF-LABEL: fsubRI_X:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: movih32 a0, 50560
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; CHECK-SF-NEXT: ori32 a0, a0, 2048
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; CHECK-SF-NEXT: fmtvrl vr1, a0
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; CHECK-SF-NEXT: fadds vr0, vr0, vr1
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fsubRI_X:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: movih32 a0, 50560
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; CHECK-SF2-NEXT: ori32 a0, a0, 2048
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; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
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; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr1
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; CHECK-SF2-NEXT: rts16
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entry:
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%fsub = fsub float %x, 4097.0
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ret float %fsub
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}
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define float @fmulRR(float %x, float %y) {
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;
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; CHECK-SF-LABEL: fmulRR:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fmuls vr0, vr1, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fmulRR:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fmul.32 vr0, vr1, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fmul = fmul float %y, %x
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ret float %fmul
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}
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define float @fnmulRR_a(float %x, float %y) {
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;
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; CHECK-SF-LABEL: fnmulRR_a:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fnmuls vr0, vr1, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fnmulRR_a:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fnmul.32 vr0, vr1, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%z = fneg float %y
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%fnmul = fmul float %z, %x
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ret float %fnmul
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}
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define float @fnmulRR_b(float %x, float %y) {
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; CHECK-SF-LABEL: fnmulRR_b:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fnmuls vr0, vr0, vr1
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fnmulRR_b:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fnmul.32 vr0, vr0, vr1
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; CHECK-SF2-NEXT: rts16
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entry:
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%z = fneg float %x
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%fnmul = fmul float %y, %z
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ret float %fnmul
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}
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define float @fmulRI(float %x) {
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;
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; CHECK-SF-LABEL: fmulRI:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: movih32 a0, 16672
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; CHECK-SF-NEXT: fmtvrl vr1, a0
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; CHECK-SF-NEXT: fmuls vr0, vr0, vr1
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fmulRI:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: movih32 a0, 16672
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; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
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; CHECK-SF2-NEXT: fmul.32 vr0, vr0, vr1
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; CHECK-SF2-NEXT: rts16
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entry:
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%fmul = fmul float %x, 10.0
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ret float %fmul
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}
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define float @fmulRI_X(float %x) {
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;
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; CHECK-SF-LABEL: fmulRI_X:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: movih32 a0, 17792
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; CHECK-SF-NEXT: ori32 a0, a0, 2048
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; CHECK-SF-NEXT: fmtvrl vr1, a0
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; CHECK-SF-NEXT: fmuls vr0, vr0, vr1
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fmulRI_X:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: movih32 a0, 17792
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; CHECK-SF2-NEXT: ori32 a0, a0, 2048
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; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
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; CHECK-SF2-NEXT: fmul.32 vr0, vr0, vr1
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; CHECK-SF2-NEXT: rts16
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entry:
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%fmul = fmul float %x, 4097.0
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ret float %fmul
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}
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define float @fdivRR(float %x, float %y) {
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;
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; CHECK-SF-LABEL: fdivRR:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fdivs vr0, vr1, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fdivRR:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fdiv.32 vr0, vr1, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fdiv = fdiv float %y, %x
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ret float %fdiv
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}
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define float @fdivRI(float %x) {
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;
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; CHECK-SF-LABEL: fdivRI:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: movih32 a0, 16672
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; CHECK-SF-NEXT: fmtvrl vr1, a0
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; CHECK-SF-NEXT: fdivs vr0, vr0, vr1
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fdivRI:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: movih32 a0, 16672
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; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
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; CHECK-SF2-NEXT: fdiv.32 vr0, vr0, vr1
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; CHECK-SF2-NEXT: rts16
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entry:
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%fdiv = fdiv float %x, 10.0
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ret float %fdiv
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}
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define float @fdivRI_X(float %x) {
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;
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; CHECK-SF-LABEL: fdivRI_X:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: movih32 a0, 17792
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; CHECK-SF-NEXT: ori32 a0, a0, 2048
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; CHECK-SF-NEXT: fmtvrl vr1, a0
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; CHECK-SF-NEXT: fdivs vr0, vr0, vr1
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fdivRI_X:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: movih32 a0, 17792
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; CHECK-SF2-NEXT: ori32 a0, a0, 2048
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; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
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; CHECK-SF2-NEXT: fdiv.32 vr0, vr0, vr1
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; CHECK-SF2-NEXT: rts16
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entry:
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%fdiv = fdiv float %x, 4097.0
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ret float %fdiv
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}
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define float @fnegRR(float %x) {
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;
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; CHECK-SF-LABEL: fnegRR:
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; CHECK-SF: # %bb.0: # %entry
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; CHECK-SF-NEXT: fnegs vr0, vr0
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; CHECK-SF-NEXT: rts16
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;
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; CHECK-SF2-LABEL: fnegRR:
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; CHECK-SF2: # %bb.0: # %entry
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; CHECK-SF2-NEXT: fneg.32 vr0, vr0
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; CHECK-SF2-NEXT: rts16
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entry:
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%fneg = fneg float %x
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ret float %fneg
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}
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