derek.holloway
7502bf64a4
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51 lines
3.1 KiB
LLVM
51 lines
3.1 KiB
LLVM
; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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; This testcase exposed a problem with a previous handling of selecting
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; constant vectors (for vdelta). Originally a bitcast of a vsplat was
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; created (both being ISD, not machine nodes). Selection of vsplat relies
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; on its return type, and there was no way to get these nodes to be
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; selected in the right order, without getting the main selection algorithm
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; confused.
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; Make sure this compiles successfully.
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; CHECK: call f1
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target triple = "hexagon"
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%s.0 = type { %s.1 }
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%s.1 = type { i32, ptr }
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%s.2 = type { i8, i8, [16 x i8], i8, [16 x i8] }
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; Function Attrs: nounwind
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define dso_local zeroext i8 @f0(i8 zeroext %a0, ptr nocapture readonly %a1, i8 signext %a2) local_unnamed_addr #0 {
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b0:
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br i1 undef, label %b2, label %b1
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b1: ; preds = %b0
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%v0 = load <64 x i8>, ptr undef, align 1
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%v1 = icmp ult <64 x i8> %v0, <i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52>
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%v2 = xor <64 x i1> %v1, zeroinitializer
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%v3 = select <64 x i1> %v2, <64 x i32> undef, <64 x i32> zeroinitializer
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%v4 = select <64 x i1> zeroinitializer, <64 x i32> <i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000>, <64 x i32> %v3
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%v5 = add <64 x i32> %v4, zeroinitializer
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br label %b2
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b2: ; preds = %b1, %b0
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%v6 = phi <64 x i32> [ undef, %b0 ], [ %v5, %b1 ]
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%v7 = add <64 x i32> %v6, undef
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%v8 = add <64 x i32> %v7, undef
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%v9 = add <64 x i32> %v8, undef
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%v10 = add <64 x i32> %v9, undef
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%v11 = add <64 x i32> %v10, undef
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%v12 = add <64 x i32> %v11, undef
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%v13 = extractelement <64 x i32> %v12, i32 0
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tail call void @f1(ptr null, i32 undef, i32 undef, i32 %v13, i32 undef) #2
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unreachable
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}
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declare dso_local void @f1(ptr, i32, i32, i32, i32) local_unnamed_addr #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
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attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
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attributes #2 = { nounwind }
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