derek.holloway
7502bf64a4
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37 lines
1.0 KiB
LLVM
37 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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; Check that gp-relative instructions are being generated.
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; CHECK: r{{[0-9]+}} = memw(gp+#g0)
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; CHECK: r{{[0-9]+}} = memw(gp+#g1)
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; CHECK: if (p{{[0-3]}}) memw(##g2) = r{{[0-9]+}}
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@g0 = common global i32 0, align 4
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@g1 = common global i32 0, align 4
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@g2 = common global i32 0, align 4
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define i32 @f0(i32 %a0) #0 {
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b0:
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%v0 = load i32, ptr @g0, align 4
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%v1 = load i32, ptr @g1, align 4
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%v2 = add nsw i32 %v1, %v0
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%v3 = icmp eq i32 %v0, %v1
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br i1 %v3, label %b2, label %b1
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b1: ; preds = %b0
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%v4 = load i32, ptr @g2, align 4
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br label %b3
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b2: ; preds = %b0
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%v5 = add nsw i32 %v2, %v0
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store i32 %v5, ptr @g2, align 4
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br label %b3
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b3: ; preds = %b2, %b1
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%v6 = phi i32 [ %v4, %b1 ], [ %v5, %b2 ]
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%v7 = icmp eq i32 %v2, %v6
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%v8 = select i1 %v7, i32 %v6, i32 %v1
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ret i32 %v8
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv5" }
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