derek.holloway
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85 lines
3.0 KiB
LLVM
85 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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; Test that we compile the HVX dual output intrinsics.
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define inreg <16 x i32> @f0(<16 x i32> %a0, <16 x i32> %a1, ptr %a2) #0 {
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; CHECK-LABEL: f0:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = #-1
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; CHECK-NEXT: v2 = vmem(r0+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q0 = vand(v2,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w = vadd(v0.w,v1.w,q0):carry
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = load <16 x i32>, ptr %a2, align 64
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%v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -1)
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%v2 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v1)
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%v3 = extractvalue { <16 x i32>, <64 x i1> } %v2, 0
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ret <16 x i32> %v3
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}
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define inreg <16 x i32> @f1(<16 x i32> %a0, <16 x i32> %a1, ptr %a2) #0 {
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; CHECK-LABEL: f1:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: r1 = #-1
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; CHECK-NEXT: v2 = vmem(r0+#0)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: q0 = vand(v2,r1)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w = vsub(v0.w,v1.w,q0):carry
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = load <16 x i32>, ptr %a2, align 64
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%v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -1)
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%v2 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32> %a0, <16 x i32> %a1, <64 x i1> %v1)
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%v3 = extractvalue { <16 x i32>, <64 x i1> } %v2, 0
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ret <16 x i32> %v3
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}
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define inreg <16 x i32> @f2(<16 x i32> %a0, <16 x i32> %a1) #0 {
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; CHECK-LABEL: f2:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w,q0 = vadd(v0.w,v1.w):carry
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarryo(<16 x i32> %a0, <16 x i32> %a1)
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%v1 = extractvalue { <16 x i32>, <64 x i1> } %v0, 0
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ret <16 x i32> %v1
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}
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define inreg <16 x i32> @f3(<16 x i32> %a0, <16 x i32> %a1) #0 {
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; CHECK-LABEL: f3:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.w,q0 = vsub(v0.w,v1.w):carry
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = tail call { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarryo(<16 x i32> %a0, <16 x i32> %a1)
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%v1 = extractvalue { <16 x i32>, <64 x i1> } %v0, 0
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ret <16 x i32> %v1
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}
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declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarry(<16 x i32>, <16 x i32>, <64 x i1>) #1
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declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarry(<16 x i32>, <16 x i32>, <64 x i1>) #1
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declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vaddcarryo(<16 x i32>, <16 x i32>) #1
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declare { <16 x i32>, <64 x i1> } @llvm.hexagon.V6.vsubcarryo(<16 x i32>, <16 x i32>) #1
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declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvxv66,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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