derek.holloway
7502bf64a4
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31 lines
1.2 KiB
LLVM
31 lines
1.2 KiB
LLVM
; RUN: llc -march=hexagon -debug-only=isel 2>&1 < %s - | FileCheck %s
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; REQUIRES: asserts
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; CHECK: [[R0:%[0-9]+]]:intregs = A2_tfrsi 0
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; CHECK-NEXT: predregs = C2_tfrrp killed [[R0]]:intregs
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define fastcc i16 @test(ptr %0, { <4 x i32>, <4 x i1> } %1, <4 x i1> %2) {
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Entry:
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%3 = alloca [16 x i8], i32 0, align 16
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%4 = alloca [16 x i8], i32 0, align 16
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store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr %4, align 16
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store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, ptr %3, align 16
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%5 = load <4 x i32>, ptr %4, align 16
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%6 = load <4 x i32>, ptr %3, align 16
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%7 = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %5, <4 x i32> %6)
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%8 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %2)
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br i1 %8, label %OverflowFail, label %OverflowOk
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OverflowFail: ; preds = %Entry
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store volatile i32 0, ptr null, align 4
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unreachable
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OverflowOk: ; preds = %Entry
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%9 = extractvalue { <4 x i32>, <4 x i1> } %7, 0
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store <4 x i32> %9, ptr %0, align 16
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ret i16 0
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}
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declare { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) #0
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declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>) #0
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