derek.holloway
7502bf64a4
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64 lines
2.1 KiB
LLVM
64 lines
2.1 KiB
LLVM
; RUN: llc -mtriple=hexagon -hexagon-expand-condsets=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
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;
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; Expand-condsets eliminates the "mux" instruction, which is what this
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; testcase is checking.
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; Test that we don't generate a new value compare if the operands are
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; the same register.
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; CHECK-NOT: cmp.eq([[REG0:(r[0-9]+)]].new,[[REG0]])
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; CHECK: cmp.eq([[REG1:(r[0-9]+)]],[[REG1]])
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%s.0 = type { i16, i8, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [2 x i32], ptr, ptr, ptr, %s.1, ptr, [8 x i8], i8 }
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%s.1 = type { i32, i16, i16 }
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@g0 = external global %s.0
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@g1 = external unnamed_addr constant [23 x i8], align 8
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; Function Attrs: nounwind
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declare void @f0(ptr nocapture, ptr nocapture readonly, ...) #0
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define void @f1() #1 {
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b0:
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%v0 = load ptr, ptr undef, align 4
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%v1 = load i32, ptr undef, align 4
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br i1 undef, label %b4, label %b1
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b1: ; preds = %b0
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%v2 = icmp slt i32 %v1, 0
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%v3 = lshr i32 %v1, 5
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%v4 = add i32 %v3, -134217728
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%v5 = select i1 %v2, i32 %v4, i32 %v3
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%v6 = getelementptr inbounds i32, ptr %v0, i32 %v5
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%v7 = icmp ult ptr %v6, %v0
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%v8 = select i1 %v7, i32 0, i32 1
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br i1 undef, label %b2, label %b4
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b2: ; preds = %b1
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%v9 = icmp slt i32 %v1, 0
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%v10 = lshr i32 %v1, 5
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%v11 = add i32 %v10, -134217728
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%v12 = select i1 %v9, i32 %v11, i32 %v10
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%v13 = getelementptr inbounds i32, ptr %v0, i32 %v12
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%v14 = icmp ult ptr %v13, %v0
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%v15 = select i1 %v14, i32 0, i32 1
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%v16 = icmp eq i32 %v8, %v15
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br i1 %v16, label %b4, label %b3
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b3: ; preds = %b2
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call void (ptr, ptr, ...) @f0(ptr @g0, ptr @g1, i32 %v8, i32 %v15) #0
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unreachable
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b4: ; preds = %b2, %b1, %b0
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br i1 undef, label %b6, label %b5
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b5: ; preds = %b4
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unreachable
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b6: ; preds = %b4
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv5" }
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attributes #1 = { "target-cpu"="hexagonv5" }
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