derek.holloway
7502bf64a4
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32 lines
874 B
LLVM
32 lines
874 B
LLVM
; RUN: llc -mtriple=hexagon -mcpu=hexagonv60 < %s | FileCheck %s
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; This test checks to see if, after lowering the two loads below, we set up the
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; memrefs of the resulting load MIs correctly, so that they are packetized
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; together.
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; CHECK: {
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; CHECK: r{{[0-9]*}} = memw(r1{{[678]}}+#0)
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; CHECK-NEXT: r{{[0-9]*}} = memw(r1{{[678]}}+#0)
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; Function Attrs: nounwind
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define i64 @f0(ptr nocapture %a0, ptr nocapture %a1, ptr nocapture %a2) #0 {
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b0:
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%v0 = tail call i32 @f1() #0
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store i32 %v0, ptr %a2, align 4, !tbaa !0
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%v1 = load i32, ptr %a0, align 4, !tbaa !0
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%v2 = sext i32 %v1 to i64
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%v3 = load i32, ptr %a1, align 4, !tbaa !0
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%v4 = sext i32 %v3 to i64
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%v5 = mul nsw i64 %v4, %v2
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ret i64 %v5
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}
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declare i32 @f1(...)
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attributes #0 = { nounwind }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"int", !2}
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!2 = !{!"omnipotent char", !3}
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!3 = !{!"Simple C/C++ TBAA"}
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