derek.holloway
7502bf64a4
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54 lines
1.6 KiB
LLVM
54 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
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; Test that the pipeliner schedules a store before the load in which there is a
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; loop carried dependence. Previously, the loop carried dependence wasn't added
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; and the load from iteration n was scheduled prior to the store from iteration
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; n-1.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: memh({{.*}}) =
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; CHECK: = memuh({{.*}})
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; CHECK: endloop0
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%s.0 = type { i16, i16 }
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; Function Attrs: nounwind
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define void @f0() local_unnamed_addr #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ 0, %b0 ], [ %v22, %b1 ]
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%v1 = load ptr, ptr undef, align 4
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%v3 = load i16, ptr %v1, align 2
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%v4 = add i16 0, %v3
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%v5 = add i16 %v4, 0
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%v6 = add i16 %v5, 0
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%v7 = add i16 %v6, 0
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%v8 = add i16 %v7, 0
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%v9 = add i16 %v8, 0
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%v10 = add i16 %v9, 0
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%v11 = add i16 %v10, 0
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%v12 = add i16 %v11, 0
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%v13 = add i16 %v12, 0
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%v14 = add i16 %v13, 0
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%v15 = add i16 %v14, 0
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%v16 = add i16 %v15, 0
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%v17 = add i16 %v16, 0
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%v18 = add i16 %v17, 0
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%v19 = add i16 %v18, 0
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%v20 = load ptr, ptr undef, align 4
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store i16 %v19, ptr undef, align 2
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%v21 = getelementptr inbounds %s.0, ptr %v20, i32 0, i32 1
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store i16 0, ptr %v21, align 2
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%v22 = add nuw nsw i32 %v0, 1
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%v23 = icmp eq i32 %v22, 6
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br i1 %v23, label %b2, label %b1
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b2: ; preds = %b1
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
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