derek.holloway
7502bf64a4
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36 lines
1.1 KiB
LLVM
36 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=hexagon -enable-pipeliner < %s
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; REQUIRES: asserts
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; Test that the pipeliner doesn't ICE in the ScheduleDAG code because
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; the latency values are not updated properly. The pipeliner should
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; not change the latency of chain edges.
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; Function Attrs: nounwind
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define void @f0() #0 {
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b0:
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%v0 = alloca [10 x i16], align 8
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br label %b1
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b1: ; preds = %b1, %b0
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%v1 = phi i32 [ %v7, %b1 ], [ undef, %b0 ]
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%v2 = add i32 %v1, -1
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%v3 = getelementptr inbounds [10 x i16], ptr %v0, i32 0, i32 %v2
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%v4 = add i32 %v1, -2
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%v5 = getelementptr inbounds [10 x i16], ptr %v0, i32 0, i32 %v4
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%v6 = load i16, ptr %v5, align 2, !tbaa !0
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store i16 %v6, ptr %v3, align 2, !tbaa !0
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%v7 = add i32 %v1, -4
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%v8 = icmp sgt i32 %v7, 3
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br i1 %v8, label %b1, label %b2
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b2: ; preds = %b2, %b1
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br label %b2
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"short", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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