derek.holloway
7502bf64a4
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37 lines
1.4 KiB
LLVM
37 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=hexagon -enable-aa-sched-mi < %s | FileCheck %s
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; The two memory addresses in the load and the memop below are trivially
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; non-aliasing. However, there are some cases where the scheduler cannot
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; determine this - in this case, it is because of the use of memops, that on the
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; surface. do not have only one mem operand. However, the backend knows MIs and
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; can step in and help some cases. In our case, if the base registers are the
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; same and the offsets different and the memory access size is such that
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; the two accesses won't overlap, we can tell the scheduler that there is no
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; dependence due to aliasing between the two instructions.
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; In the example below, this allows the load to be packetized with the memop.
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; CHECK: {
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; CHECK: r{{[0-9]*}} = memw(r{{[0-9]*}}+#4)
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; CHECK-NEXT: memw(r{{[0-9]*}}+#0) += #3
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; CHECK: }
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@g0 = common global [10 x i32] zeroinitializer, align 8
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; Function Attrs: nounwind
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define void @f0(ptr nocapture %a0) #0 {
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b0:
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%v0 = load i32, ptr %a0, align 4, !tbaa !0
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%v1 = add nsw i32 %v0, 3
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store i32 %v1, ptr %a0, align 4, !tbaa !0
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%v2 = getelementptr inbounds i32, ptr %a0, i32 1
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%v3 = load i32, ptr %v2, align 4, !tbaa !0
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store i32 %v3, ptr @g0, align 8, !tbaa !0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"int", !2}
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!2 = !{!"omnipotent char", !3}
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!3 = !{!"Simple C/C++ TBAA"}
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