derek.holloway
7502bf64a4
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32 lines
930 B
LLVM
32 lines
930 B
LLVM
; RUN: llc -mtriple=hexagon < %s
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; REQUIRES: asserts
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; Check that llc does not crash.
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@g0 = private unnamed_addr constant [7 x i8] c"%d\09\09%d\00", align 1
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@g1 = common global <4 x i32> zeroinitializer, align 16
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declare i32 @f0(...)
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; Function Attrs: nounwind
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define i32 @f1() #0 {
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b0:
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%v0 = alloca i32, align 4
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%v1 = alloca i32, align 4
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%v2 = alloca [0 x <4 x i32>], align 16
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store i32 0, ptr %v0
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store i32 0, ptr %v1, align 4
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call void @llvm.memset.p0.i32(ptr align 16 %v2, i8 0, i32 0, i1 false)
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%v4 = load i32, ptr %v1, align 4
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%v5 = add nsw i32 %v4, 1
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store i32 %v5, ptr %v1, align 4
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%v6 = load <4 x i32>, ptr @g1, align 16
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%v7 = call i32 @f0(ptr @g0, i32 %v5, <4 x i32> %v6)
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ret i32 0
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}
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; Function Attrs: argmemonly nounwind
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declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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attributes #1 = { argmemonly nounwind }
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